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path: root/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
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* Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not passJim Grosbach2010-03-271-2/+2
| | | | | | | through to the generic version. The generic functions use STR/LDR, but T2 needs the t2STR/t2LDR instead so we get the addressing mode correct. llvm-svn: 99678
* Fix a crash compiling 254.gap for Thumb2. The Thumb2 add/sub with 12-bitBob Wilson2010-03-081-5/+23
| | | | | | | | immediate instructions cannot set the condition codes, so they do not have the extra cc_out operand. We hit an assertion during tail duplication because the instruction being duplicated had more operands that expected. llvm-svn: 98001
* Handle AddrMode6 (for NEON load/stores) in Thumb2's rewriteT2FrameIndex.Bob Wilson2010-02-061-11/+10
| | | | | | Radar 7614112. llvm-svn: 95456
* Remove predicates when changing an add into an unpredicable mov.Jakob Stoklund Olesen2010-01-191-3/+7
| | | | | | | Since the mov is executed unconditionally, make sure that the add didn't have any predicate. llvm-svn: 93909
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-24/+0
| | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. llvm-svn: 90634
* Refactor code.Evan Cheng2009-11-081-53/+0
| | | | llvm-svn: 86423
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-1/+1
| | | | llvm-svn: 86408
* t2ldrpci_pic can be used for blockaddress as well.Evan Cheng2009-11-071-3/+14
| | | | llvm-svn: 86400
* Refactor code. Fix a potential missing check. Teach isIdentical() about ↵Evan Cheng2009-11-071-26/+0
| | | | | | tLDRpci_pic. llvm-svn: 86330
* - Add TargetInstrInfo::isIdentical(). It's similar to MachineInstr::isIdenticalEvan Cheng2009-11-071-0/+26
| | | | | | | | | | except it doesn't care if the definitions' virtual registers differ. This is used by machine LICM and other MI passes to perform CSE. - Teach Thumb2InstrInfo::isIdentical() to check two t2LDRpci_pic are identical. Since pc relative constantpool entries are always different, this requires it it check if the values can actually the same. llvm-svn: 86328
* - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng2009-11-061-1/+43
| | | | | | | | | | | | load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. llvm-svn: 86304
* Use NEON reg-reg moves, where profitable. This reduces "domain-cross" ↵Anton Korobeynikov2009-11-021-1/+2
| | | | | | stalls, when we used to mix vfp and neon code (the former were used for reg-reg moves) llvm-svn: 85764
* Fix a couple more places where we are creating ld / st instructions without ↵Evan Cheng2009-11-011-2/+18
| | | | | | memoperands. llvm-svn: 85746
* Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate theBob Wilson2009-10-281-0/+1
| | | | | | | opcode and operand with a tab. Check for these instructions in the usual places. llvm-svn: 85411
* Handle AddrMode4 for Thumb2 in rewriteT2FrameIndex. This occurs forBob Wilson2009-09-151-0/+5
| | | | | | | | | | | VLDM/VSTM instructions, and without this check, the code assumes that an offset is allowed, as it would be with VLDR/VSTR. The asm printer, however, silently drops the offset, producing incorrect code. Since the address register in this case is either the stack or frame pointer, the spill location ends up conflicting with some other stack slot or with outgoing arguments on the stack. llvm-svn: 81879
* Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which ↵Evan Cheng2009-08-271-14/+22
| | | | | | cannot fold any immediate offset. llvm-svn: 80191
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-4/+4
| | | | llvm-svn: 78666
* Always use the 16-bit tMOVgpr2gpr instead of the 32-bit t2MOVr.Evan Cheng2009-08-101-2/+1
| | | | llvm-svn: 78549
* Use 16-bit tMOVgpr2gpr instead of tMOVr to copy GPR registers in Thumb2 mode.Evan Cheng2009-08-071-6/+1
| | | | llvm-svn: 78398
* It turns out most of the thumb2 instructions are not allowed to touch SP. ↵Evan Cheng2009-08-071-28/+70
| | | | | | | | | | The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time. This fixes PR4659 and PR4682. llvm-svn: 78361
* Use the i12 variant of load / store opcodes if offset is zero. Now we pass ↵Evan Cheng2009-08-031-1/+5
| | | | | | all of multisource as well. llvm-svn: 77939
* Move the getInlineAsmLength virtual method from TAI to TII, whereChris Lattner2009-08-021-2/+1
| | | | | | | | | | the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. llvm-svn: 77877
* Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte ↵Evan Cheng2009-07-291-0/+2
| | | | | | / halfword. llvm-svn: 77422
* Thumb-2: fix typo that caused incorrect stack elimination for VFP operations ↵David Goodwin2009-07-281-1/+1
| | | | | | and very large stack frames. llvm-svn: 77401
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-12/+317
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* More DCE.Evan Cheng2009-07-271-4/+0
| | | | llvm-svn: 77231
* Get rid of more dead code.Evan Cheng2009-07-271-2/+0
| | | | llvm-svn: 77227
* Get rid of some more getOpcode calls.Evan Cheng2009-07-271-3/+0
| | | | | | This also fixes potential problems in ARMBaseInstrInfo routines not recognizing thumb1 instructions when 32-bit and 16-bit instructions mix. llvm-svn: 77218
* Use t2LDRi12 and t2STRi12 to load / store to / from stack frames. Eliminate ↵Evan Cheng2009-07-271-2/+33
| | | | | | more getOpcode calls. llvm-svn: 77181
* Use the right instructions to copy between GPR and the more strictive tGPR ↵Evan Cheng2009-07-271-4/+11
| | | | | | classes. t2MOV does not match the RC requirements. llvm-svn: 77175
* Get rid of a couple of unnecessary getOpcode calls.Evan Cheng2009-07-251-1/+1
| | | | llvm-svn: 77035
* Change Thumb2 jumptable codegen to one that uses two level jumps:Evan Cheng2009-07-251-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: adr r12, #LJTI3_0_0 ldr pc, [r12, +r0, lsl #2] LJTI3_0_0: .long LBB3_24 .long LBB3_30 .long LBB3_31 .long LBB3_32 After: adr r12, #LJTI3_0_0 add pc, r12, +r0, lsl #2 LJTI3_0_0: b.w LBB3_24 b.w LBB3_30 b.w LBB3_31 b.w LBB3_32 This has several advantages. 1. This will make it easier to optimize this to a TBB / TBH instruction + (smaller) table. 2. This eliminate the need for ugly asm printer hack to force the address into thumb addresses (bit 0 is one). 3. Same codegen for pic and non-pic. 4. This eliminate the need to align the table so constantpool island pass won't have to over-estimate the size. Based on my calculation, the later is probably slightly faster as well since ldr pc with shifter address is very slow. That is, it should be a win as long as the HW implementation can do a reasonable job of branch predict the second branch. llvm-svn: 77024
* Clean up.Evan Cheng2009-07-241-3/+1
| | | | llvm-svn: 76984
* FLDD, FLDS, FCPYD, FCPYS, FSTD, FSTS, VMOVD, VMOVQ maps to the same ↵Evan Cheng2009-07-241-8/+0
| | | | | | instructions on all sub-targets. llvm-svn: 76925
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-25/+4
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Fix frame index elimination to correctly handle thumb-2 addressing modes ↵David Goodwin2009-07-231-0/+23
| | | | | | that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. llvm-svn: 76883
* Emit cross regclass register moves for thumb2.Anton Korobeynikov2009-07-161-0/+21
| | | | | | Minor code duplication cleanup. llvm-svn: 76124
* Major changes to Thumb (not Thumb2). Many 16-bit instructions either ↵Evan Cheng2009-07-111-6/+3
| | | | | | | | modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well. llvm-svn: 75359
* t2LDM_RET does not fall-through.David Goodwin2009-07-101-1/+1
| | | | llvm-svn: 75250
* Use common code for both ARM and Thumb-2 instruction and register info.David Goodwin2009-07-081-283/+1
| | | | llvm-svn: 75067
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-0/+1
| | | | llvm-svn: 75036
* Checkpoint Thumb2 Instr info work. Generalized base code so that it can be ↵David Goodwin2009-07-081-37/+98
| | | | | | shared between ARM and Thumb2. Not yet activated because register information must be generalized first. llvm-svn: 75010
* Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into ↵David Goodwin2009-07-021-0/+312
Thumb1InstrInfo, Thumb2InstrInfo, Thumb1RegisterInfo and Thumb2RegisterInfo. Move methods from ARMInstrInfo to ARMBaseInstrInfo to prepare for sharing with Thumb2. llvm-svn: 74731
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