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path: root/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp
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* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-2/+2
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Simplify check that optional def is there and is CPSR.Bill Wendling2011-10-111-5/+4
| | | | llvm-svn: 141602
* If the CPSR is defined by a copy, then we don't want to merge it into an ITBill Wendling2011-10-101-0/+22
| | | | | | | | | | | | | | | | | | | | | block. E.g., if we have: movs r1, r1 rsb r1, 0 movs r2, r2 rsb r2, 0 we don't want this to be converted to: movs r1, r1 movs r2, r2 itt mi rsb r1, 0 rsb r2, 0 PR11107 & <rdar://problem/10259534> llvm-svn: 141589
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-301-3/+0
| | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. llvm-svn: 134204
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* Use a small local function for a single remaining late isMoveInstr call inJakob Stoklund Olesen2010-07-161-24/+42
| | | | | | Thumb2ITBlockPass. llvm-svn: 108564
* Remove early IT block formation. It's not used.Evan Cheng2010-07-021-204/+5
| | | | llvm-svn: 107513
* Remove pointless variable LastDef.Duncan Sands2010-06-291-2/+0
| | | | llvm-svn: 107135
* minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. ↵Jim Grosbach2010-06-281-1/+1
| | | | | | No functional change. llvm-svn: 106988
* Thumb2ITBlockPass: Fix a possible dereference of an invalid iterator. This wasDaniel Dunbar2010-06-251-2/+2
| | | | | | | | | introduced in r106343, but only showed up recently (with a particular compiler & linker combination) because of the particular check, and because we have no builtin checking for dereferencing the end of an array, which is truly unfortunate. llvm-svn: 106908
* Tail merging pass shall not break up IT blocks. rdar://8115404Evan Cheng2010-06-221-13/+6
| | | | llvm-svn: 106517
* Fix a crash caused by dereference of MBB.end(). rdar://8110842Evan Cheng2010-06-201-6/+8
| | | | llvm-svn: 106399
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-181-25/+98
| | | | | | | | | | | | | | | | - This fixed a number of bugs in if-converter, tail merging, and post-allocation scheduler. If-converter now runs branch folding / tail merging first to maximize if-conversion opportunities. - Also changed the t2IT instruction slightly. It now defines the ITSTATE register which is read by instructions in the IT block. - Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't change the instruction ordering in the IT block (since IT mask has been finalized). It also ensures no other instructions can be scheduled between instructions in the IT block. This is not yet enabled. llvm-svn: 106344
* Delete code that's not safe.Evan Cheng2010-06-101-13/+0
| | | | llvm-svn: 105774
* Allow target to place 2-address pass inserted copies in better spots. Thumb2 ↵Evan Cheng2010-06-091-12/+4
| | | | | | will use this to try to avoid breaking up IT blocks. llvm-svn: 105745
* Thumb2 IT blocks are fairly expensive. When there are multiple selects usingEvan Cheng2010-06-091-12/+281
| | | | | | | | | | | | | | | the same condition, it's important to make sure they are scheduled together to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms IT blocks early (by re-scheduling instructions and split basic blocks) to attempt to fix this. This is not turned on by default since I am not sure this is the right fix. Another issue is llvm selects are modeled as two-address conditional moves. This can be very bad when the copies before the conditional moves are not coalesced away. Teach IT formation pass to move the copies above the IT block (when legal) to avoid breaking the IT block. llvm-svn: 105669
* Handle dbg_value instructions (i.e., skip them) when generating IT blocks.Jim Grosbach2010-06-071-3/+4
| | | | | | rdar://7797940 llvm-svn: 105557
* Fixed a bug in the IT mask printing where T means the cond bit in the maskJohnny Chen2010-03-171-3/+5
| | | | | | | | | | | | | | matches that of Firstcond[0] and E means otherwise. The Firstcond[0] is also tagged in the Mask to facilitate Asm printing. The disassembler also depends on this arrangement. This is similar to what's described in A2.5.2 ITSTATE. Ran: utils/lit/lit.py test/CodeGen/ARM test/CodeGen/Thumb test/CodeGen/Thumb2 successfully. llvm-svn: 98775
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-161-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-161-3/+5
| | | | | | | | | | | | | | | | | | (RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-1/+1
| | | | llvm-svn: 86408
* - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng2009-11-061-42/+0
| | | | | | | | | | | | load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. llvm-svn: 86304
* Remove includes of Support/Compiler.h that are no longer needed after theNick Lewycky2009-10-251-1/+0
| | | | | | VISIBILITY_HIDDEN removal. llvm-svn: 85043
* Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.Nick Lewycky2009-10-251-1/+1
| | | | | | | Chris claims we should never have visibility_hidden inside any .cpp file but that's still not true even after this commit. llvm-svn: 85042
* Branches must be the last instruction in a Thumb2 IT block. Approved by Evan ↵Sandeep Patel2009-10-151-1/+5
| | | | | | Cheng. llvm-svn: 84212
* Fix Thumb2 IT block pass bug. t2MOVi32imm may not be the start of a IT block.Evan Cheng2009-09-281-21/+42
| | | | llvm-svn: 83008
* Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudoEvan Cheng2009-09-281-6/+31
| | | | | | | | | instruction. This makes it re-materializable. Thumb2 will split it back out into two instructions so IT pass will generate the right mask. Also, this expose opportunies to optimize the movw to a 16-bit move. llvm-svn: 82982
* Turn on if-conversion for thumb2.Evan Cheng2009-08-151-12/+8
| | | | llvm-svn: 79084
* I can type.Evan Cheng2009-08-081-1/+1
| | | | llvm-svn: 78453
* Fix a bunch of namespace pollution.Dan Gohman2009-08-071-2/+2
| | | | llvm-svn: 78363
* Don't put IT instruction before conditional branches.Evan Cheng2009-07-111-5/+13
| | | | llvm-svn: 75361
* Add a thumb2 pass to insert IT blocks.Evan Cheng2009-07-101-0/+108
llvm-svn: 75218
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