summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/Thumb1RegisterInfo.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* rdar://7937137 - dbg values not being handled in thumb1 version ofJim Grosbach2010-05-041-0/+7
| | | | | | eliminateFrameIndex(), leading to llvm_unreachable() assertion failure. llvm-svn: 102980
* ReuseFrameIndexVals is used in multiple files, so it can't be static.Dan Gohman2010-04-151-1/+4
| | | | llvm-svn: 101379
* Add const qualifiers to CodeGen's use of LLVM IR constructs.Dan Gohman2010-04-151-1/+1
| | | | llvm-svn: 101334
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-3/+2
| | | | llvm-svn: 100214
* Change ARM ld/st multiple instructions to have variant instructions forBob Wilson2010-03-131-3/+2
| | | | | | | | | | | | | | | writebacks to the address register. This gets rid of the hack that the first register on the list was the magic writeback register operand. There was an implicit constraint that if that operand was not reg0 it had to match the base register operand. The post-RA scheduler's antidependency breaker did not understand that constraint and sometimes changed one without the other. This also fixes Radar 7495976 and should help the verifier work better for ARM code. There are now new ld/st instructions explicit writeback operands and explicit constraints that tie those registers together. llvm-svn: 98409
* comment why we use custom epilogue for t1 functions using vaargs.Jim Grosbach2010-03-101-0/+5
| | | | llvm-svn: 98182
* Clear up the last (famous last words) frame index value reuse issues for Thumb1.Jim Grosbach2010-03-101-1/+1
| | | | llvm-svn: 98109
* Change the Value argument to eliminateFrameIndex to a type-tagged value. ThisJim Grosbach2010-03-091-2/+3
| | | | | | | | | | is preparatory to having PEI's scavenged frame index value reuse logic properly distinguish types of frame values (e.g., whether the value is stack-pointer relative or frame-pointer relative). No functionality change. llvm-svn: 98086
* scavenged frame index value re-use gets confused when more than one baseJim Grosbach2010-03-091-0/+7
| | | | | | | | register is involved for thumb1. Work around this for the moment by only re-using SP-relative offsets. This is temporary 'til the code can distinguish multiple base registers. llvm-svn: 98071
* Thumb1 epilogue code generation needs to take into account that callee-savedJim Grosbach2010-03-061-4/+18
| | | | | | | registers may be restored via a pop instruction, not just a tRestore. This fixes nightly test 471.omnetep for Thumb1. llvm-svn: 97867
* handle very large call frames when require SPAdj != 0 for Thumb1Jim Grosbach2010-02-241-3/+3
| | | | llvm-svn: 97013
* Remove predicates when changing an add into an unpredicable mov.Jakob Stoklund Olesen2010-01-191-2/+6
| | | | | | | Since the mov is executed unconditionally, make sure that the add didn't have any predicate. llvm-svn: 93909
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-1/+1
| | | | | | Patch by Howard Hinnant! llvm-svn: 90365
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-1/+1
| | | | llvm-svn: 86494
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-2/+3
| | | | llvm-svn: 86408
* Cleanup now that frame index scavenging via post-pass is working for ARM and ↵Jim Grosbach2009-10-281-12/+0
| | | | | | Thumb2. llvm-svn: 85406
* Trim more includes.Evan Cheng2009-10-221-1/+0
| | | | llvm-svn: 84832
* Missing piece of the ARM frame index post-scavenging conditionalizationJim Grosbach2009-10-211-0/+12
| | | | llvm-svn: 84798
* Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*Jim Grosbach2009-10-201-12/+0
| | | | | | functions are not needed. llvm-svn: 84587
* Enable allocation of R3 in Thumb1Jim Grosbach2009-10-191-1/+0
| | | | llvm-svn: 84563
* Adjust the scavenge register spilling to allow the target to choose anJim Grosbach2009-10-191-15/+32
| | | | | | | | | | appropriate restore location for the spill as well as perform the actual save and restore. The Thumb1 target uses this to make sure R12 is not clobbered while a spilled scavenger register is live there. llvm-svn: 84554
* Cleanup up unused R3LiveIn tracking.Jim Grosbach2009-10-081-9/+0
| | | | llvm-svn: 83522
* Re-enable register scavenging in Thumb1 by default.Jim Grosbach2009-10-081-64/+9
| | | | llvm-svn: 83521
* reverting thumb1 scavenging default due to test failure while I figure out ↵Jim Grosbach2009-10-071-8/+64
| | | | | | what's up. llvm-svn: 83501
* Enable thumb1 register scavenging by default.Jim Grosbach2009-10-071-64/+8
| | | | llvm-svn: 83494
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-13/+19
| | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. llvm-svn: 83467
* In Thumb1, the register scavenger is not always able to use an emergencyJim Grosbach2009-10-051-0/+25
| | | | | | | | spill slot. When frame references are via the frame pointer, they will be negative, but Thumb1 load/store instructions only allow positive immediate offsets. Instead, Thumb1 will spill to R12. llvm-svn: 83336
* ARM::tPOP and tPOP_RET each has an extra writeback operand now.Evan Cheng2009-10-011-0/+1
| | | | llvm-svn: 83214
* Start of revamping the register scavenging in PEI. ARM Thumb1 is the drivingJim Grosbach2009-09-241-53/+83
| | | | | | | | | | | | | | | | | | | interest for this, as it currently reserves a register rather than using the scavenger for matierializing constants as needed. Instead of scavenging registers on the fly while eliminating frame indices, new virtual registers are created, and then a scavenged collectively in a post-pass over the function. This isolates the bits that need to interact with the scavenger, and sets the stage for more intelligent use, and reuse, of scavenged registers. For the time being, this is disabled by default. Once the bugs are worked out, the current scavenging calls in replaceFrameIndices() will be removed and the post-pass scavenging will be the default. Until then, -enable-frame-index-scavenging enables the new code. Currently, only the Thumb1 back end is set up to use it. llvm-svn: 82734
* Remove some unused variables and methods warned about byDuncan Sands2009-09-061-2/+1
| | | | | | icc (#177, partial). Patch by Erick Tryzelaar. llvm-svn: 81106
* Push LLVMContexts through the IntegerType APIs.Owen Anderson2009-08-131-1/+2
| | | | llvm-svn: 78948
* Shrinkify Thumb2 load / store multiple instructions.Evan Cheng2009-08-111-1/+1
| | | | llvm-svn: 78717
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-1/+1
| | | | llvm-svn: 78666
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-1/+1
| | | | | | own struct type. llvm-svn: 78610
* tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.Evan Cheng2009-07-281-0/+5
| | | | llvm-svn: 77305
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-2/+2
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a ↵Evan Cheng2009-07-261-8/+8
| | | | | | low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir. llvm-svn: 77172
* Refactor. Get rid of a few more getOpcode() calls.Evan Cheng2009-07-261-0/+1
| | | | llvm-svn: 77164
* Revert the ConstantInt constructors back to their 2.5 forms where possible, ↵Owen Anderson2009-07-241-2/+1
| | | | | | thanks to contexts-on-types. More to come. llvm-svn: 77011
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-0/+9
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Get rid of the Pass+Context magic.Owen Anderson2009-07-221-1/+1
| | | | llvm-svn: 76702
* Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub ↵Evan Cheng2009-07-201-3/+11
| | | | | | fp, #c. llvm-svn: 76401
* Fix a regression from 76124. Thumb1 instructions default to S bit being true.Evan Cheng2009-07-191-13/+14
| | | | llvm-svn: 76374
* Emit cross regclass register moves for thumb2.Anton Korobeynikov2009-07-161-10/+0
| | | | | | Minor code duplication cleanup. llvm-svn: 76124
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-6/+8
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* Move EVER MORE stuff over to LLVMContext.Owen Anderson2009-07-141-1/+4
| | | | llvm-svn: 75703
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-1/+1
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* Major changes to Thumb (not Thumb2). Many 16-bit instructions either ↵Evan Cheng2009-07-111-28/+96
| | | | | | | | modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically. A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well. llvm-svn: 75359
* Implement changes from Chris's feedback.Torok Edwin2009-07-081-0/+1
| | | | | | Finish converting lib/Target. llvm-svn: 75043
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-5/+6
| | | | llvm-svn: 75036
OpenPOWER on IntegriCloud