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* Refactor data-in-code annotations.Jim Grosbach2012-05-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach2012-05-152-0/+3
| | | | | | | | Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
* Nuke a few dead remnants of the CBE.Jim Grosbach2012-05-051-27/+0
| | | | llvm-svn: 156241
* Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bitsKevin Enderby2012-05-031-31/+57
| | | | | | | | | for the assembler and disassembler. Which were not being set/read correctly for offsets greater than 22 bits in some cases. Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles! llvm-svn: 156118
* ARM: allow vanilla expressions for movw/movt.Jim Grosbach2012-05-011-4/+16
| | | | | | | | | | Expressions for movw/movt don't always have an :upper16: or :lower16: on them and that's ok. When they don't, it's just a plain [0-65536] immediate result, effectively the same as a :lower16: variant kind. rdar://10550147 llvm-svn: 155941
* ARM: Diagnostics for out of range fixups.Jim Grosbach2012-04-301-34/+52
| | | | | | | | | | | Replace some assert() calls w/ actual diagnostics. In a perfect world, there'd be range checks on these values long before things ever reached this code. For now, though, issuing a better-late-than-never diagnostic is still a big improvement over assert(). rdar://11347287 llvm-svn: 155851
* - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng2012-04-271-10/+22
| | | | | | | | instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 llvm-svn: 155685
* ARM: Thumb ldr(literal) base address alignment is 32-bits.Jim Grosbach2012-04-261-1/+2
| | | | | | | | | | The base address for the PC-relative load is Align(PC,4), so it's the address of the word containing the 16-bit instruction, not the address of the instruction itself. Ugh. rdar://11314619 llvm-svn: 155659
* If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng2012-04-262-6/+15
| | | | | | | | | | the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
* Unify internal representation of ARM instructions with a register ↵Richard Barton2012-04-251-2/+1
| | | | | | right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. llvm-svn: 155565
* ARM 'adr' fixups don't need the interworking addend tweaking.Jim Grosbach2012-04-121-0/+3
| | | | | | | | They reference the PC directly, so things work properly that way. rdar://11231229 llvm-svn: 154576
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ↵Craig Topper2012-04-021-1/+2
| | | | | | getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
* ARM fix encoding fixup resolution for ldrd and friends.Jim Grosbach2012-03-301-0/+2
| | | | | | | | | The 8-bit payload is not contiguous in the opcode. Move the upper nibble over 4 bits into the correct place. rdar://11158641 llvm-svn: 153780
* Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy2012-03-305-10/+33
| | | | | | | | fixup_arm_condbranch. Patch by Tim Northover! llvm-svn: 153737
* Prune some includesCraig Topper2012-03-271-1/+0
| | | | llvm-svn: 153502
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-2/+2
| | | | llvm-svn: 153500
* Prune some includes and forward declarations.Craig Topper2012-03-262-0/+2
| | | | llvm-svn: 153429
* ARM non-scattered MachO relocations for movw/movt.Jim Grosbach2012-03-201-22/+58
| | | | | | | | Needed when building -mdynamic-no-pic code. rdar://10459256 llvm-svn: 153097
* ARM branch relaxation for unconditional t1 branches.Jim Grosbach2012-03-191-0/+11
| | | | | | rdar://11059157 llvm-svn: 153055
* ARM don't use MCRelaxAll, as it's not safe on ARM.Jim Grosbach2012-03-081-2/+2
| | | | | | | | | The ARM code generator makes aggressive assumptions about the encodings being selected for branches which MCRelaxAll invalidates. rdar://11006355 llvm-svn: 152268
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-061-15/+31
| | | | | | Register pair, all lanes subscripting. llvm-svn: 152157
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-0/+17
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-051-1/+2
| | | | | | | Used to allow context sensitive printing of super-register or sub-register references. llvm-svn: 152043
* ARM BL/BLX instruction fixups should use relocations.Jim Grosbach2012-02-275-10/+43
| | | | | | | | | | | | | We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 llvm-svn: 151571
* comment fixJia Liu2012-02-241-1/+1
| | | | llvm-svn: 151339
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-1/+0
| | | | llvm-svn: 150918
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-185-5/+5
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Revert r150222, as the clang driver now handles this properly.Jim Grosbach2012-02-101-11/+3
| | | | | | | Now that the clang driver passes the CPU and feature information to the backend when processing assembly files (150273), this isn't necessary. llvm-svn: 150274
* ARM on darwin, v6 implies the presence of VFP for the assembler.Jim Grosbach2012-02-101-3/+11
| | | | | | rdar://10838899 llvm-svn: 150222
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-074-15/+13
| | | | llvm-svn: 149961
* Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM ↵James Molloy2012-01-281-1/+1
| | | | | | | | and MIPS ELF backends. Fixes PR11877 llvm-svn: 149180
* Better user diagnostics for more ARM MachO relocation errors.Jim Grosbach2012-01-271-4/+8
| | | | llvm-svn: 149102
* Keep source information, if available, around for ARM Fixups.Jim Grosbach2012-01-262-9/+14
| | | | | | | | | | | | | | | | | Adjust an example MachObjectWriter diagnostic to use the information to issue a better message. Before: LLVM ERROR: unknown ARM fixup kind! After: x.s:6:5: error: unsupported relocation on symbol beq bar ^ rdar://9800182 llvm-svn: 149093
* Add support for the R_ARM_TARGET1 relocation, which should be given to ↵James Molloy2012-01-261-1/+4
| | | | | | | | relocations applied to all C++ constructors and destructors. This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against. llvm-svn: 149057
* Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson2012-01-241-1/+1
| | | | | | accomodate every target I can think of offhand. llvm-svn: 148833
* Revert r148686 (and r148694, a fix to it) due to a serious layeringChandler Carruth2012-01-241-2/+5
| | | | | | | | | | | | | | | | | | violation -- MC cannot depend on CodeGen. Specifically, the MCTargetDesc component of each target is actually a subcomponent of the MC library. As such, it cannot depend on the target-independent code generator, because MC itself cannot depend on the target-independent code generator. This change moved a flag from the ARM MCTargetDesc file ARMMCAsmInfo.cpp to the CodeGen layer in ARMException.cpp, leaving behind an 'extern' to refer back to it. That layering order isn't viable givin the constraints outlined above. Commandline flags are designed to be static specifically to avoid these types of bugs. Fixing this is likely going to require some non-trivial refactoring. llvm-svn: 148759
* An option to selectively enable parts of ARM EHABI support.Evgeniy Stepanov2012-01-231-5/+2
| | | | | | | | This change adds an new value to the --arm-enable-ehabi option that disables emitting unwinding descriptors. This mode gives a working backtrace() without the (currently broken) exception support. llvm-svn: 148686
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-203-5/+2
| | | | llvm-svn: 148578
* Silence warnings about mixing enums.Benjamin Kramer2012-01-191-3/+2
| | | | llvm-svn: 148495
* Thumb2 relaxation for tADR to t2ADR.Jim Grosbach2012-01-191-0/+2
| | | | llvm-svn: 148456
* Add comment and fix range check in condition.Jim Grosbach2012-01-191-1/+3
| | | | llvm-svn: 148455
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-181-0/+1
| | | | | | | | Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 llvm-svn: 148432
* Thumb2 relaxation for LDR(literal).Jim Grosbach2012-01-181-9/+20
| | | | | | | | | If the fixup is out of range for the Thumb1 instruction, relax it to the Thumb2 encoding instead. rdar://10711829 llvm-svn: 148424
* Tidy up. MCAsmBackend naming conventions.Jim Grosbach2012-01-181-11/+11
| | | | llvm-svn: 148400
* Thumb2 load/store fixups don't set the thumb bit.Jim Grosbach2012-01-181-4/+8
| | | | | | | | | | Load/store instructions w/ a fixup to be relative a function marked as thumb don't use the low bit to specify thumb vs. non-thumb like interworking branches do, so don't set it when dealing with those fixups. rdar://10348687. llvm-svn: 148366
* Move some ARM specific MCAssmebler bits into the ARMAsmBackend.Jim Grosbach2012-01-181-0/+15
| | | | llvm-svn: 148364
* Move default case for covered enum outside of switch.Richard Smith2012-01-101-1/+1
| | | | llvm-svn: 147870
* Fix a -Wreturn-type warning in g++.Richard Smith2012-01-101-0/+1
| | | | llvm-svn: 147867
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-102-3/+0
| | | | llvm-svn: 147855
* Fix incorrect relocation generation. Patch by Kristof Beyls.Rafael Espindola2011-12-221-8/+1
| | | | | | Fixes PR11214. llvm-svn: 147180
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