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* Make Triple's isOSBinFormatXXX functions partition triple-space.Tim Northover2013-12-101-1/+1
| | | | | | | | | | | Most users would be surprised if "isCOFF" and "isMachO" were simultaneously true, unless they'd put the compiler in a box with a gun attached to a photon detector. This makes sure precisely one of the three formats is true for any triple and simplifies some target logic based on that. llvm-svn: 196934
* ARM: Add subtarget feature for CRCBernard Ogden2013-10-291-2/+2
| | | | | | | | Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend. Differential Revision: http://llvm-reviews.chandlerc.com/D2036 llvm-svn: 193599
* Add subtarget feature support for Cortex-A53Bernard Ogden2013-10-141-2/+7
| | | | | | | Some previous implicit defaults have changed, for example FP and NEON are now on by default. llvm-svn: 192590
* Add a MCTargetStreamer interface.Rafael Espindola2013-10-081-0/+4
| | | | | | | | | | | | | This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. llvm-svn: 192181
* [ARM] Improve build attributes emission.Amara Emerson2013-10-071-1/+1
| | | | llvm-svn: 192111
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-051-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. llvm-svn: 192035
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-031-0/+11
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191885
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-261-1/+1
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191428
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-171-8/+25
| | | | llvm-svn: 190862
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-1/+17
| | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. llvm-svn: 190598
* Add a subtarget feature 'v8' to the ARM backend.Joey Gouly2013-06-261-1/+4
| | | | | | This allows for targeting the ARMv8 AArch32 variant. llvm-svn: 184967
* ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.Tim Northover2013-06-101-0/+2
| | | | | | | | | | | Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some only support Thumb mode (M-class ones currently). This makes sure such CPUs default to the correct mode and makes the AsmParser diagnose an attempt to switch modes incorrectly. rdar://14024354 llvm-svn: 183710
* Follow up of the introduction of MCSymbolizer.Quentin Colombet2013-05-241-4/+5
| | | | | | | - Ressurect old MCDisassemble API to soften transition. - Extend MCTargetDesc to set target specific symbolizer. llvm-svn: 182688
* MC: Disassembled CFG reconstruction.Ahmed Bougacha2013-05-241-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch builds on some existing code to do CFG reconstruction from a disassembled binary: - MCModule represents the binary, and has a list of MCAtoms. - MCAtom represents either disassembled instructions (MCTextAtom), or contiguous data (MCDataAtom), and covers a specific range of addresses. - MCBasicBlock and MCFunction form the reconstructed CFG. An MCBB is backed by an MCTextAtom, and has the usual successors/predecessors. - MCObjectDisassembler creates a module from an ObjectFile using a disassembler. It first builds an atom for each section. It can also construct the CFG, and this splits the text atoms into basic blocks. MCModule and MCAtom were only sketched out; MCFunction and MCBB were implemented under the experimental "-cfg" llvm-objdump -macho option. This cleans them up for further use; llvm-objdump -d -cfg now generates graphviz files for each function found in the binary. In the future, MCObjectDisassembler may be the right place to do "intelligent" disassembly: for example, handling constant islands is just a matter of splitting the atom, using information that may be available in the ObjectFile. Also, better initial atom formation than just using sections is possible using symbols (and things like Mach-O's function_starts load command). This brings two minor regressions in llvm-objdump -macho -cfg: - The printing of a relocation's referenced symbol. - An annotation on loop BBs, i.e., which are their own successor. Relocation printing is replaced by the MCSymbolizer; the basic CFG annotation will be superseded by more related functionality. llvm-svn: 182628
* Add MCSymbolizer for symbolic/annotated disassembly.Ahmed Bougacha2013-05-241-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a basic first step towards symbolization of disassembled instructions. This used to be done using externally provided (C API) callbacks. This patch introduces: - the MCSymbolizer class, that mimics the same functions that were used in the X86 and ARM disassemblers to symbolize immediate operands and to annotate loads based off PC (for things like c string literals). - the MCExternalSymbolizer class, which implements the old C API. - the MCRelocationInfo class, which provides a way for targets to translate relocations (either object::RelocationRef, or disassembler C API VariantKinds) to MCExprs. - the MCObjectSymbolizer class, which does symbolization using what it finds in an object::ObjectFile. This makes simple symbolization (with no fancy relocation stuff) work for all object formats! - x86-64 Mach-O and ELF MCRelocationInfos. - A basic ARM Mach-O MCRelocationInfo, that provides just enough to support the C API VariantKinds. Most of what works in otool (the only user of the old symbolization API that I know of) for x86-64 symbolic disassembly (-tvV) works, namely: - symbol references: call _foo; jmp 15 <_foo+50> - relocations: call _foo-_bar; call _foo-4 - __cf?string: leaq 193(%rip), %rax ## literal pool for "hello" Stub support is the main missing part (because libObject doesn't know, among other things, about mach-o indirect symbols). As for the MCSymbolizer API, instead of relying on the disassemblers to call the tryAdding* methods, maybe this could be done automagically using InstrInfo? For instance, even though PC-relative LEAs are used to get the address of string literals in a typical Mach-O file, a MOV would be used in an ELF file. And right now, the explicit symbolization only recognizes PC-relative LEAs. InstrInfo should have already have most of what is needed to know what to symbolize, so this can definitely be improved. I'd also like to remove object::RelocationRef::getValueString (it seems only used by relocation printing in objdump), as simply printing the created MCExpr is definitely enough (and cleaner than string concats). llvm-svn: 182625
* Remove the MachineMove class.Rafael Espindola2013-05-131-1/+1
| | | | | | | | | | | | It was just a less powerful and more confusing version of MCCFIInstruction. A side effect is that, since MCCFIInstruction uses dwarf register numbers, calls to getDwarfRegNum are pushed out, which should allow further simplifications. I left the MachineModuleInfo::addFrameMove interface unchanged since this patch was already fairly big. llvm-svn: 181680
* Remove unused argument.Rafael Espindola2013-05-101-1/+1
| | | | llvm-svn: 181618
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-301-1/+11
| | | | | | | | More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien llvm-svn: 173943
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-021-1/+1
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
* Remove duplicate includes.Roman Divacky2012-12-211-1/+0
| | | | llvm-svn: 170902
* MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach2012-12-191-1/+1
| | | | | | | | | MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. llvm-svn: 170610
* Added Mapping Symbols for ARM ELFTim Northover2012-12-071-1/+4
| | | | | | | | | | Before this patch, when you objdump an LLVM-compiled file, objdump tried to decode data-in-code sections as if they were code. This patch adds the missing Mapping Symbols, as defined by "ELF for the ARM Architecture" (ARM IHI 0044D). Patch based on work by Greg Fitzgerald. llvm-svn: 169609
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-1/+1
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Add LLVM support for Swift.Bob Wilson2012-09-291-0/+8
| | | | llvm-svn: 164899
* - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2Evan Cheng2012-04-271-10/+22
| | | | | | | | instructions. - However, it does support dmb, dsb, isb, mrs, and msr. rdar://11331541 llvm-svn: 155685
* If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng2012-04-261-5/+14
| | | | | | | | | | the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ↵Craig Topper2012-04-021-1/+2
| | | | | | getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
* ARM don't use MCRelaxAll, as it's not safe on ARM.Jim Grosbach2012-03-081-2/+2
| | | | | | | | | The ARM code generator makes aggressive assumptions about the encodings being selected for branches which MCRelaxAll invalidates. rdar://11006355 llvm-svn: 152268
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-051-1/+2
| | | | | | | Used to allow context sensitive printing of super-register or sub-register references. llvm-svn: 152043
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-1/+0
| | | | llvm-svn: 150918
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Revert r150222, as the clang driver now handles this properly.Jim Grosbach2012-02-101-11/+3
| | | | | | | Now that the clang driver passes the CPU and feature information to the backend when processing assembly files (150273), this isn't necessary. llvm-svn: 150274
* ARM on darwin, v6 implies the presence of VFP for the assembler.Jim Grosbach2012-02-101-3/+11
| | | | | | rdar://10838899 llvm-svn: 150222
* Sink codegen optimization level into MCCodeGenInfo along side relocation modelEvan Cheng2011-11-161-2/+3
| | | | | | | and code model. This eliminates the need to pass OptLevel flag all over the place and makes it possible for any codegen pass to use this information. llvm-svn: 144788
* Remove NaClModeDavid Meyer2011-10-181-8/+0
| | | | llvm-svn: 142338
* ARM Darwin default relocation model is PIC.Jim Grosbach2011-09-301-2/+5
| | | | | | | This matches clang, so default options in llc and friends are now closer to clang's defaults. llvm-svn: 140863
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-281-4/+7
| | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. llvm-svn: 140696
* ARMv7a has the PKH instructions.Jim Grosbach2011-09-141-2/+2
| | | | llvm-svn: 139753
* Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ↵James Molloy2011-09-071-2/+3
| | | | | | handling to llvm-mc. Reviewed by Owen Anderson. llvm-svn: 139237
* Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certainNick Lewycky2011-09-051-0/+8
| | | | | | | instructions are more aligned than the CPU requires, and adds some additional directives, to follow in future patches. Patch by David Meyer! llvm-svn: 139125
* Fix typo in comment.Nick Lewycky2011-09-051-1/+1
| | | | llvm-svn: 139122
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Some refactoring so TargetRegistry.h no longer has to include any filesEvan Cheng2011-08-231-5/+8
| | | | | | from MC. llvm-svn: 138367
* The new ARM disassembler disassembles "bx lr" as a special BX_ret ↵Benjamin Kramer2011-08-091-10/+0
| | | | | | instruction so target specific analysis isn't needed anymore. llvm-svn: 137151
* Add MCInstrAnalysis class. This allows the targets to specify own versions ↵Benjamin Kramer2011-08-081-0/+53
| | | | | | | | | of MCInstrDescs functions. - Add overrides for ARM. - Teach llvm-objdump to use this instead of plain MCInstrDesc. llvm-svn: 137059
* Rename createCodeEmitter to createMCCodeEmitter; createObjectStreamer to ↵Evan Cheng2011-07-261-5/+5
| | | | | | createMCObjectStreamer. llvm-svn: 136031
* Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to ↵Evan Cheng2011-07-251-5/+5
| | | | | | createMCAsmBackend. llvm-svn: 136010
* Separate MCInstPrinter registration from AsmPrinter registration.Evan Cheng2011-07-251-0/+13
| | | | llvm-svn: 135974
* Sink ARM mc routines into MCTargetDesc.Evan Cheng2011-07-231-2/+37
| | | | llvm-svn: 135825
* Combine all MC initialization routines into one. e.g. InitializeX86MCAsmInfo,Evan Cheng2011-07-221-25/+21
| | | | | | InitializeX86MCInstrInfo, etc. are combined into InitializeX86TargetMC. llvm-svn: 135812
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