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authorTim Northover <tnorthover@apple.com>2013-06-10 23:20:58 +0000
committerTim Northover <tnorthover@apple.com>2013-06-10 23:20:58 +0000
commita2292d0b8fb291fa15b41b4f256f576abe965e98 (patch)
tree42537548c6b6d4922561466a95aae5905de728c6 /llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
parent7ed1dbfff4fe745df0247b4857d303545f90f0e6 (diff)
downloadbcm5719-llvm-a2292d0b8fb291fa15b41b4f256f576abe965e98.tar.gz
bcm5719-llvm-a2292d0b8fb291fa15b41b4f256f576abe965e98.zip
ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.
Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some only support Thumb mode (M-class ones currently). This makes sure such CPUs default to the correct mode and makes the AsmParser diagnose an attempt to switch modes incorrectly. rdar://14024354 llvm-svn: 183710
Diffstat (limited to 'llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp')
-rw-r--r--llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
index 164f57b2d05..14fd03fad8e 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp
@@ -61,6 +61,7 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
unsigned SubVer = TT[Idx];
if (SubVer >= '7' && SubVer <= '9') {
if (Len >= Idx+2 && TT[Idx+1] == 'm') {
+ isThumb = true;
if (NoCPU)
// v7m: FeatureNoARM, FeatureDB, FeatureHWDiv, FeatureMClass
ARMArchFeature = "+v7,+noarm,+db,+hwdiv,+mclass";
@@ -99,6 +100,7 @@ std::string ARM_MC::ParseARMTriple(StringRef TT, StringRef CPU) {
if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2')
ARMArchFeature = "+v6t2";
else if (Len >= Idx+2 && TT[Idx+1] == 'm') {
+ isThumb = true;
if (NoCPU)
// v6m: FeatureNoARM, FeatureMClass
ARMArchFeature = "+v6,+noarm,+mclass";
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