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path: root/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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* Fix undefined behavior (negation of INT_MIN) in ARM backend.Richard Smith2012-08-241-1/+1
| | | | llvm-svn: 162520
* Remove getARMRegisterNumbering and replace with calls intoEric Christopher2012-08-091-32/+34
| | | | | | | | | | | the register info for getEncodingValue. This builds on the small patch of yesterday to set HWEncoding in the register file. One (deprecated) use was turned into a hard number to avoid needing register info in the old JIT. llvm-svn: 161628
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-021-7/+17
| | | | llvm-svn: 161159
* Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach2012-05-151-0/+1
| | | | | | | | Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
* ARM: allow vanilla expressions for movw/movt.Jim Grosbach2012-05-011-4/+16
| | | | | | | | | | Expressions for movw/movt don't always have an :upper16: or :lower16: on them and that's ok. When they don't, it's just a plain [0-65536] immediate result, effectively the same as a :lower16: variant kind. rdar://10550147 llvm-svn: 155941
* Unify internal representation of ARM instructions with a register ↵Richard Barton2012-04-251-2/+1
| | | | | | right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. llvm-svn: 155565
* Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy2012-03-301-2/+6
| | | | | | | | fixup_arm_condbranch. Patch by Tim Northover! llvm-svn: 153737
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-2/+2
| | | | llvm-svn: 153500
* ARM BL/BLX instruction fixups should use relocations.Jim Grosbach2012-02-271-8/+15
| | | | | | | | | | | | | We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 llvm-svn: 151571
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-3/+3
| | | | llvm-svn: 149961
* Keep source information, if available, around for ARM Fixups.Jim Grosbach2012-01-261-6/+6
| | | | | | | | | | | | | | | | | Adjust an example MachObjectWriter diagnostic to use the information to issue a better message. Before: LLVM ERROR: unknown ARM fixup kind! After: x.s:6:5: error: unsupported relocation on symbol beq bar ^ rdar://9800182 llvm-svn: 149093
* Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson2012-01-241-1/+1
| | | | | | accomodate every target I can think of offhand. llvm-svn: 148833
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-3/+1
| | | | llvm-svn: 148578
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-181-0/+1
| | | | | | | | Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 llvm-svn: 148432
* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-101-1/+0
| | | | llvm-svn: 147855
* ARM assembly parsing and encoding support for LDRD(label).Jim Grosbach2011-12-191-1/+14
| | | | | | rdar://9932658 llvm-svn: 146921
* ARM NEON relax parse time diagnostics for alignment specifiers.Jim Grosbach2011-12-191-4/+4
| | | | | | | There's more variation that we need to handle. Error checking will need to be on operand predicates. llvm-svn: 146884
* ARM encoder method needs the physical register number, not the enum.Jim Grosbach2011-12-021-1/+1
| | | | llvm-svn: 145711
* Fix encoding of Thumb2 shifted register operands with RRX shifts.Owen Anderson2011-09-131-0/+1
| | | | llvm-svn: 139606
* Zap some junk from the ARM instruction descriptions.Eli Friedman2011-09-131-14/+0
| | | | llvm-svn: 139575
* Fix encoding of PC-relative LDRSHW with an immediate offset.Owen Anderson2011-09-121-10/+19
| | | | llvm-svn: 139537
* Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.Owen Anderson2011-09-091-1/+6
| | | | llvm-svn: 139422
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-0/+20
| | | | llvm-svn: 139381
* Thumb2 assembly parsing and encoding for LDRD(immediate).Jim Grosbach2011-09-081-0/+41
| | | | | | Refactor operand handling for STRD as well. Tests for that forthcoming. llvm-svn: 139322
* Fix encoding for tBcc with immediate offset operand.Owen Anderson2011-08-311-1/+5
| | | | llvm-svn: 138889
* Fix roundtripping of Thumb BL/BLX instructions with immediate offsets ↵Owen Anderson2011-08-311-3/+31
| | | | | | instead of labels. llvm-svn: 138874
* Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather ↵Owen Anderson2011-08-301-1/+4
| | | | | | than labels. llvm-svn: 138837
* Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets ↵Owen Anderson2011-08-301-1/+4
| | | | | | instead of labels. llvm-svn: 138835
* Fix encoding of Thumb1 B instructions with immediate offsets, which is ↵Owen Anderson2011-08-301-1/+4
| | | | | | necessary for round-tripping. llvm-svn: 138834
* Clean up whitespace.Owen Anderson2011-08-301-8/+8
| | | | llvm-svn: 138833
* Improve handling of #-0 offsets for many more pre-indexed addressing modes.Owen Anderson2011-08-291-1/+3
| | | | llvm-svn: 138754
* Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson2011-08-261-1/+15
| | | | | | decoding bug this uncovered. llvm-svn: 138675
* Correct encoding of BL with immediate offset.Owen Anderson2011-08-261-5/+10
| | | | llvm-svn: 138673
* Support an extension of ARM asm syntax to allow immediate operands to ADR ↵Owen Anderson2011-08-261-9/+22
| | | | | | instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. llvm-svn: 138635
* ARM clean up the imm_sr operand class representation.Jim Grosbach2011-08-171-10/+0
| | | | | | | | | Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. llvm-svn: 137879
* Correct immediate range for shifter operands. Patch by James Molloy, with ↵Owen Anderson2011-08-111-1/+4
| | | | | | additional encoding fixes added by me. llvm-svn: 137322
* Fix encodings for Thumb ASR and LSR immediate operands. They encode the ↵Owen Anderson2011-08-081-0/+13
| | | | | | range 1-32, with 32 encoded as 0. llvm-svn: 137062
* ARM simplify the postidx_reg operand encoding.Jim Grosbach2011-08-051-2/+1
| | | | | | | The immediate portion of the operand is just a boolean (the 'U' bit indicating add vs. subtract). Treat it as such. llvm-svn: 136969
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-0/+16
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* Update comments.Owen Anderson2011-07-281-18/+10
| | | | llvm-svn: 136367
* Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng2011-07-271-5/+0
| | | | | | | | | This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 llvm-svn: 136292
* ARM parsing and encoding of SBFX and UBFX.Jim Grosbach2011-07-271-5/+0
| | | | | | | | | Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. llvm-svn: 136264
* ARM cleanup of rot_imm encoding.Jim Grosbach2011-07-261-11/+0
| | | | | | | | Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
* Sink ARM mc routines into MCTargetDesc.Evan Cheng2011-07-231-0/+1339
llvm-svn: 135825
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