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* ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach2011-10-071-0/+1
| | | | llvm-svn: 141446
* ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach2011-09-301-2/+1
| | | | | | | | | | | Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 llvm-svn: 140834
* Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix ↵Owen Anderson2011-09-211-1/+0
| | | | | | other test failures I caused. llvm-svn: 140284
* Print out immediate offset versions of PC-relative load/store instructions ↵Owen Anderson2011-09-211-0/+2
| | | | | | as [pc, #123] rather than simply #123. llvm-svn: 140283
* Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach2011-09-191-0/+2
| | | | llvm-svn: 140078
* Don't attach annotations to MCInst's. Instead, have the disassembler ↵Owen Anderson2011-09-151-1/+1
| | | | | | return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. llvm-svn: 139876
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-0/+2
| | | | llvm-svn: 139381
* Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= ↵James Molloy2011-09-071-2/+2
| | | | | | handling to llvm-mc. Reviewed by Owen Anderson. llvm-svn: 139237
* ARM clean up the imm_sr operand class representation.Jim Grosbach2011-08-171-0/+1
| | | | | | | | | Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. llvm-svn: 137879
* ARM use a dedicated printer for postidx_reg operands.Jim Grosbach2011-08-051-0/+1
| | | | llvm-svn: 136968
* LDCL_POST and STCL_POST need one's-complement offsets, rather than two's ↵Owen Anderson2011-08-041-0/+2
| | | | | | complement offsets. Add an appropriate immediate type for them. llvm-svn: 136896
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-3/+4
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* ARM cleanup of rot_imm encoding.Jim Grosbach2011-07-261-0/+1
| | | | | | | | Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
* ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach2011-07-251-1/+1
| | | | llvm-svn: 136006
* ARM SSAT instruction 5-bit immediate handling.Jim Grosbach2011-07-221-0/+1
| | | | | | | | | The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-1/+2
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-201-0/+2
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* Simplify printing of ARM shifted immediates.Jim Grosbach2011-07-111-2/+0
| | | | | | | | | Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
* createMCInstPrinter doesn't need TargetMachine anymore.Evan Cheng2011-07-061-2/+1
| | | | llvm-svn: 134525
* Don't hardcode the %reg format in the streamer.Rafael Espindola2011-06-021-1/+1
| | | | llvm-svn: 132451
* - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes2011-04-041-0/+5
| | | | | | | | | | also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
* Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes2011-03-311-0/+4
| | | | | | | | | | | | | | all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
* Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes2011-03-311-4/+0
| | | | llvm-svn: 128635
* Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes2011-03-311-0/+4
| | | | | | | | | | | | | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128632
* Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"Matt Beaumont-Gay2011-03-311-8/+2
| | | | | | This revision introduced a dependency cycle, as nlewycky mentioned by email. llvm-svn: 128597
* - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT andBruno Cardoso Lopes2011-03-301-2/+8
| | | | | | | | | | | | | | | {STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser llvm-svn: 128585
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-241-0/+1
| | | | llvm-svn: 128236
* We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling2011-03-211-2/+5
| | | | | | | | | the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. llvm-svn: 127986
* Remove some dead patterns.Jim Grosbach2011-03-141-2/+0
| | | | llvm-svn: 127601
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-051-0/+1
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. llvm-svn: 127101
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-141-0/+2
| | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
* Add support to the ARM MC infrastructure to support mcr and friends. This ↵Owen Anderson2011-01-131-0/+2
| | | | | | | | | | | | | | requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-8/+8
| | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
* Pseudo-ize Thumb2 jump tables with explicit MC lowering to the rawJim Grosbach2010-11-291-4/+0
| | | | | | instructions. This simplifies instruction printing and disassembly. llvm-svn: 120333
* ARM Pseudo-ize tBR_JTr.Jim Grosbach2010-11-291-1/+0
| | | | llvm-svn: 120310
* stub out a powerpc MCInstPrinter implementation.Chris Lattner2010-11-141-1/+1
| | | | llvm-svn: 119059
* For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled ↵Evan Cheng2010-11-121-1/+0
| | | | | | with movi + orr. llvm-svn: 118945
* Remove unused function.Jim Grosbach2010-11-031-1/+0
| | | | llvm-svn: 118141
* Remove the no longer used 'Modifier' optional operand to the ARMJim Grosbach2010-11-031-8/+4
| | | | | | printOperand() asm printer helper functions. rdar://8425198 llvm-svn: 118140
* Remove unused function.Jim Grosbach2010-11-031-2/+0
| | | | llvm-svn: 118139
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-031-1/+1
| | | | | | | parts. Represent the operation mode as an optional operand instead. rdar://8614429 llvm-svn: 118137
* hook up getOpcodeName for ARM so that "llc -show-mc-inst" includesChris Lattner2010-10-281-0/+3
| | | | | | | | | | | | | | | the opcode string in the inst dump, e.g.: vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec] @ <MCInst #989 VMOVRRD @ <MCOperand Reg:68> @ <MCOperand Reg:69> @ <MCOperand Reg:19> @ <MCOperand Imm:14> @ <MCOperand Reg:0>> The "VMOVRRD" is new. llvm-svn: 117609
* imm12 operands aren't Thumb2 only, so rename the printer helper function.Jim Grosbach2010-10-251-2/+2
| | | | llvm-svn: 117291
* Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach2010-10-131-0/+1
| | | | | | | and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. llvm-svn: 116432
* PrintSpecial() can go away now.Jim Grosbach2010-10-011-1/+0
| | | | llvm-svn: 115376
* Rename the AsmPrinter directory to InstPrinter for those targets that haveJim Grosbach2010-10-011-0/+117
been MC-ized for assembly printing. MSP430 is mostly so, but still has the asm printer and lowering code in the printer subdir for the moment. llvm-svn: 115360
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