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* ARM cleanup of rot_imm encoding.Jim Grosbach2011-07-261-0/+14
| | | | | | | | Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
* ARM assembly parsing and encoding for SSAT16 instruction.Jim Grosbach2011-07-251-2/+2
| | | | llvm-svn: 136006
* ARM assembly parsing and encoding for SSAT instruction.Jim Grosbach2011-07-251-14/+6
| | | | | | | | | | | | Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the shift operand to correctly handle the allowed shift types and immediate ranges and issue meaningful diagnostics when an illegal value or shift type is specified. Add aliases to parse an ommitted shift operand (default value of 'lsl #0'). Add tests for diagnostics and proper encoding. llvm-svn: 135990
* Sink ARM mc routines into MCTargetDesc.Evan Cheng2011-07-231-1/+1
| | | | llvm-svn: 135825
* ARM SSAT instruction 5-bit immediate handling.Jim Grosbach2011-07-221-0/+6
| | | | | | | | | The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield. Update the representation such that we store the operand as 0-31, allowing us to remove the encoder method and the special case handling in the disassembler. Update the assembly parser and the instruction printer accordingly. llvm-svn: 135823
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-17/+42
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. llvm-svn: 135636
* ARM PKH shift ammount operand printing tweaks.Jim Grosbach2011-07-201-0/+19
| | | | | | | | | | Move the shift operator and special value (32 encoded as 0 for PKHTB) handling into the instruction printer. This cleans up a bit of the disassembler special casing for these instructions, more easily handles not printing the operand at all for "lsl #0" and prepares for correct asm parsing of these operands. llvm-svn: 135626
* Tweak ARM assembly parsing and printing of MSR instruction.Jim Grosbach2011-07-191-2/+15
| | | | | | | | The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. llvm-svn: 135532
* Revamp our handling of tLDMIA[_UPD] and tSTMIA[_UPD] to avoid having ↵Owen Anderson2011-07-181-0/+23
| | | | | | multiple instructions with the same encoding. This resolves another conflict when bringing up the new-style disassembler. llvm-svn: 135442
* Flesh out ARM Parser support for shifted-register operands.Jim Grosbach2011-07-131-0/+2
| | | | | | | Now works for parsing register shifted register and register shifted immediate arithmetic instructions, including the 'rrx' rotate with extend. llvm-svn: 135049
* Simplify printing of ARM shifted immediates.Jim Grosbach2011-07-111-32/+0
| | | | | | | | | Print shifted immediate values directly rather than as a payload+shifter value pair. This makes for more readable output assembly code, simplifies the instruction printer, and is consistent with how Thumb immediates are displayed. llvm-svn: 134902
* Don't hardcode the %reg format in the streamer.Rafael Espindola2011-06-021-2/+2
| | | | llvm-svn: 132451
* Constants with multiple encodings (ARM):Johnny Chen2011-04-051-2/+3
| | | | | | | | | | An alternative syntax is available for a modified immediate constant that permits the programmer to specify the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where: <byte> is the numeric value of abcdefgh, in the range 0-255 <rot> is twice the numeric value of rotation, an even number in the range 0-30. llvm-svn: 128897
* - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes2011-04-041-5/+45
| | | | | | | | | | also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. llvm-svn: 128832
* Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes2011-03-311-8/+46
| | | | | | | | | | | | | | all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128689
* Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes2011-03-311-46/+8
| | | | llvm-svn: 128635
* Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes2011-03-311-8/+46
| | | | | | | | | | | | | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases llvm-svn: 128632
* Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"Matt Beaumont-Gay2011-03-311-49/+8
| | | | | | This revision introduced a dependency cycle, as nlewycky mentioned by email. llvm-svn: 128597
* - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT andBruno Cardoso Lopes2011-03-301-8/+49
| | | | | | | | | | | | | | | {STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser llvm-svn: 128585
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-241-0/+6
| | | | llvm-svn: 128236
* Remove some dead patterns.Jim Grosbach2011-03-141-10/+0
| | | | llvm-svn: 127601
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-051-0/+3
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. llvm-svn: 127101
* Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes2011-02-181-1/+8
| | | | | | testcases for the disassembler to make sure it still works for "msr". llvm-svn: 125948
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-141-20/+12
| | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. llvm-svn: 125489
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-3/+0
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Add support for printing out floating point values from the ARM assemblyBill Wendling2011-01-261-2/+27
| | | | | | | parser. The parser will always give us a binary representation of the floating point number. llvm-svn: 124318
* Revert 124230. It was causing test failures.Bill Wendling2011-01-251-4/+2
| | | | llvm-svn: 124233
* The floating point value is encoded in its binary form as an Imm. Convert itBill Wendling2011-01-251-2/+4
| | | | | | appropriately so that it prints out the decimal representation. llvm-svn: 124230
* Add support to the ARM MC infrastructure to support mcr and friends. This ↵Owen Anderson2011-01-131-0/+10
| | | | | | | | | | | | | | requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. llvm-svn: 123404
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-25/+29
| | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-0/+3
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's theJim Grosbach2010-12-031-0/+4
| | | | | | 32-bit wide version by adding the .w suffix. llvm-svn: 120838
* Pseudo-ize Thumb2 jump tables with explicit MC lowering to the rawJim Grosbach2010-11-291-8/+0
| | | | | | instructions. This simplifies instruction printing and disassembly. llvm-svn: 120333
* Rename t2 TBB and TBH instructions to reference that they encode the jump tableJim Grosbach2010-11-291-1/+1
| | | | | | data. Next up, pseudo-izing them. llvm-svn: 120320
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-36/+24
| | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
* Minor cleanups:Bill Wendling2010-11-131-6/+8
| | | | | | | - Get the opcode once. - Add a ParserMatchClass to reglist. llvm-svn: 118997
* For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled ↵Evan Cheng2010-11-121-8/+0
| | | | | | with movi + orr. llvm-svn: 118945
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-031-1/+1
| | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
* Remove unused function.Jim Grosbach2010-11-031-8/+0
| | | | llvm-svn: 118141
* Remove the no longer used 'Modifier' optional operand to the ARMJim Grosbach2010-11-031-9/+4
| | | | | | printOperand() asm printer helper functions. rdar://8425198 llvm-svn: 118140
* Remove unused function.Jim Grosbach2010-11-031-10/+0
| | | | llvm-svn: 118139
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-031-13/+4
| | | | | | | parts. Represent the operation mode as an optional operand instead. rdar://8614429 llvm-svn: 118137
* hook up getOpcodeName for ARM so that "llc -show-mc-inst" includesChris Lattner2010-10-281-0/+6
| | | | | | | | | | | | | | | the opcode string in the inst dump, e.g.: vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec] @ <MCInst #989 VMOVRRD @ <MCOperand Reg:68> @ <MCOperand Reg:69> @ <MCOperand Reg:19> @ <MCOperand Imm:14> @ <MCOperand Reg:0>> The "VMOVRRD" is new. llvm-svn: 117609
* PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.Jim Grosbach2010-10-281-2/+5
| | | | llvm-svn: 117571
* LDRi12 machine instructions handle negative offset operands normally (simpleJim Grosbach2010-10-271-2/+5
| | | | | | integer values), not with the addrmode2 encoding. llvm-svn: 117429
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-0/+5
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* imm12 operands aren't Thumb2 only, so rename the printer helper function.Jim Grosbach2010-10-251-3/+2
| | | | llvm-svn: 117291
* Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach2010-10-131-0/+9
| | | | | | | and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. llvm-svn: 116432
* Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).Jim Grosbach2010-10-061-4/+2
| | | | llvm-svn: 115845
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