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* Replace the existing ARM disassembler with a new one based on the ↵Owen Anderson2011-08-091-337/+0
| | | | | | | | | | FixedLenDecoderEmitter. This new disassembler can correctly decode all the testcases that the old one did, though some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in operand checking as the old one was. llvm-svn: 137144
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-2/+3
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* Print out a debug message when the reglist fails the sanity check for Thumb ↵Johnny Chen2011-04-121-0/+25
| | | | | | Ld/St Multiple. llvm-svn: 129365
* Trivial comment fix.Johnny Chen2011-04-111-1/+1
| | | | llvm-svn: 129288
* Adding support for printing operands symbolically to llvm's public 'C'Kevin Enderby2011-04-111-1/+44
| | | | | | | | | | | | | disassembler API. Hooked this up to the ARM target so such tools as Darwin's otool(1) can now print things like branch targets for example this: blx _puts instead of this: blx #-36 And even print the expression encoded in the Mach-O relocation entried for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 129284
* RFE encoding should also specify the "should be" encoding bits.Johnny Chen2011-04-041-0/+6
| | | | | | | | | rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while doing regression testings. llvm-svn: 128859
* hopefully fix a problem building on cygwin-1.5Chris Lattner2010-09-071-2/+2
| | | | llvm-svn: 113255
* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-111-30/+29
| | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. llvm-svn: 110754
* prune #includes a little.Chris Lattner2010-07-201-1/+2
| | | | llvm-svn: 108929
* Reapply r105521, this time appending "LLU" to 64 bitBruno Cardoso Lopes2010-06-081-4/+4
| | | | | | immediates to avoid breaking the build. llvm-svn: 105652
* revert r105521, which is breaking the buildbots with stuff like this:Chris Lattner2010-06-051-4/+4
| | | | | | | | | | | | | | In file included from X86InstrInfo.cpp:16: X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type llvm-svn: 105524
* Initial AVX support for some instructions. No patterns matchedBruno Cardoso Lopes2010-06-051-4/+4
| | | | | | yet, only assembly encoding support. llvm-svn: 105521
* Thumb instructions which have reglist operands at the end and predicate operandsJohnny Chen2010-04-211-0/+6
| | | | | | | | before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. llvm-svn: 101974
* Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()Johnny Chen2010-04-141-3/+9
| | | | | | | | | | | | | | was asserting because the (RegClass, RegNum) combination doesn't make sense from an encoding point of view. Since getRegisterEnum() is used all over the place, to change the code to check for encoding error after each call would not only bloat the code, but also make it less readable. An Err flag is added to the ARMBasicMCBuilder where a client can set a non-zero value to indicate some kind of error condition while building up the MCInst. ARMBasicMCBuilder::BuildIt() checks this flag and returns false if a non-zero value is detected. llvm-svn: 101290
* Fixed an assert() exposed by fuzzing. Now, instead of assert when an invalidJohnny Chen2010-04-141-10/+12
| | | | | | | instruction encoding is encountered, we just return a NULL ARMBasicMCBuilder instance and the client just returns false to indicate disassembly error. llvm-svn: 101201
* Re-apply 100265 but instead disable building of ARM disassembly for now.Evan Cheng2010-04-051-46/+9
| | | | llvm-svn: 100379
* Reverting 100265 to try to get buildbots green again. Lots of self-hosting ↵Evan Cheng2010-04-051-9/+46
| | | | | | buildbots started complaining since this commit. Also xfail ARM disassembly tests. llvm-svn: 100378
* Get rid of the middleman (ARMAlgorithm), which causes more trouble than theJohnny Chen2010-04-031-46/+9
| | | | | | | abstraction it brings. And also get rid of the atexit() handler, it does not belong in the lib directory. :-) llvm-svn: 100265
* Register ARMAlgorithm::DoCleanup() to be called on exit to free the memoryJohnny Chen2010-04-031-0/+3
| | | | | | occuplied by the cached ARMAlgorithm objects. llvm-svn: 100258
* Fix another build warning.Johnny Chen2010-04-021-0/+2
| | | | llvm-svn: 100251
* Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgenJohnny Chen2010-04-021-0/+280
| | | | | | | | | | backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-161-301/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-161-0/+301
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
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