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path: root/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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* Fix typo in the comment.Johnny Chen2011-04-191-1/+1
| | | | llvm-svn: 129837
* Adding support for printing operands symbolically to llvm's public 'C'Kevin Enderby2011-04-111-0/+8
| | | | | | | | | | | | | disassembler API. Hooked this up to the ARM target so such tools as Darwin's otool(1) can now print things like branch targets for example this: blx _puts instead of this: blx #-36 And even print the expression encoded in the Mach-O relocation entried for things like this: movt r0, :upper16:((_foo-_bar)+1234) llvm-svn: 129284
* Fixed the t2PLD and friends disassembly and add two test cases.Johnny Chen2011-03-261-2/+35
| | | | llvm-svn: 128322
* Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!Johnny Chen2011-03-241-3/+1
| | | | llvm-svn: 128241
* Plug a leak in the arm disassembler and put the tests back.Benjamin Kramer2011-03-241-3/+2
| | | | llvm-svn: 128238
* For ARM Disassembler, start a newline to dump the opcode and friends for an ↵Johnny Chen2011-03-221-1/+1
| | | | | | | | instruction. Change inspired by llvm-bug 9530 submitted by Jyun-Yan You. llvm-svn: 128122
* LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.Johnny Chen2011-03-091-0/+3
| | | | | | | | | The insufficient encoding information of the combined instruction confuses the decoder wrt UQADD16. Add extra logic to recover from that. Fixed an assert reported by Sean Callanan llvm-svn: 127354
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-7/+7
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. llvm-svn: 125127
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-5/+5
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* Add correct encodings for STRD and LDRD, including fixup support. ↵Owen Anderson2010-12-011-3/+0
| | | | | | Additionally, update these to unified syntax. llvm-svn: 120589
* Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. ↵Owen Anderson2010-11-301-35/+0
| | | | | | | | | This allows the Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free. It also allows us to fold away at least one codegen-only pattern. llvm-svn: 120481
* Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng2010-11-031-6/+6
| | | | llvm-svn: 118152
* Detabify and clean up 80 column violations.Jim Grosbach2010-10-131-1/+2
| | | | llvm-svn: 116454
* Add ARM Disassembler to the CMake build.Oscar Fuentes2010-09-281-2/+2
| | | | llvm-svn: 114949
* ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to ↵NAKAMURA Takumi2010-09-081-2/+2
| | | | | | Cygwin-1.5, following up to r113255. llvm-svn: 113345
* The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .tdJohnny Chen2010-08-121-0/+7
| | | | | | | | | | entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2. Recover by looking for ARM:USAT encoding pattern before delegating to the auto- gened decoder. Added a "usat" test case to arm-tests.txt. llvm-svn: 110894
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-111-1/+1
| | | | | | instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
* For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if ↵Johnny Chen2010-04-201-5/+5
| | | | | | | | | Rn(Inst{19-16})=='1111', transform the Opcode to the corresponding t2LDR*pci counterpart. Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT llvm-svn: 101915
* More IT instruction error-handling improvements from fuzzing.Johnny Chen2010-04-201-3/+17
| | | | llvm-svn: 101839
* Better error handling of invalid IT mask '0000', instead of just asserting.Johnny Chen2010-04-191-3/+9
| | | | llvm-svn: 101827
* Fixed logic error. Should check Builder for validity before calling SetSessionJohnny Chen2010-04-161-3/+2
| | | | | | on it. llvm-svn: 101563
* Fixed another assert exposed by fuzzing. The utility function getRegisterEnum()Johnny Chen2010-04-141-1/+1
| | | | | | | | | | | | | | was asserting because the (RegClass, RegNum) combination doesn't make sense from an encoding point of view. Since getRegisterEnum() is used all over the place, to change the code to check for encoding error after each call would not only bloat the code, but also make it less readable. An Err flag is added to the ARMBasicMCBuilder where a client can set a non-zero value to indicate some kind of error condition while building up the MCInst. ARMBasicMCBuilder::BuildIt() checks this flag and returns false if a non-zero value is detected. llvm-svn: 101290
* Fixed a nasty layering violation in the edis sourceSean Callanan2010-04-131-2/+11
| | | | | | | | | | | | | | | code. It used to #include the enhanced disassembly information for the targets it supported straight out of lib/Target/{X86,ARM,...} but now it uses a new interface provided by MCDisassembler, and (so far) implemented by X86 and ARM. Also removed hacky #define-controlled initialization of targets in edis. If clients only want edis to initialize a limited set of targets, they can set --enable-targets on the configure command line. llvm-svn: 101179
* Get rid of traling whitespaces. No functionality change.Johnny Chen2010-04-051-1/+1
| | | | llvm-svn: 100404
* The disassembler impl. of MCDisassembler::getInstruction() was using the patternJohnny Chen2010-04-051-5/+23
| | | | | | | | | | | | | uint32_t insn; MemoryObject.readBytes(Address, 4, (uint8_t*)&insn, NULL) to read 4 bytes of memory contents into a 32-bit uint variable. This leaves the interpretation of byte order up to the host machine and causes PPC test cases of arm-tests, neon-tests, and thumb-tests to fail. Fixed to use a byte array for reading the memory contents and shift the bytes into place for the 32-bit uint variable in the ARM case and 16-bit halfword in the Thumb case. llvm-svn: 100403
* Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgenJohnny Chen2010-04-021-0/+532
| | | | | | | | | | backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. llvm-svn: 100233
* --- Reverse-merging r98637 into '.':Bob Wilson2010-03-161-513/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U test/CodeGen/ARM/tls2.ll U test/CodeGen/ARM/arm-negative-stride.ll U test/CodeGen/ARM/2009-10-30.ll U test/CodeGen/ARM/globals.ll U test/CodeGen/ARM/str_pre-2.ll U test/CodeGen/ARM/ldrd.ll U test/CodeGen/ARM/2009-10-27-double-align.ll U test/CodeGen/Thumb2/thumb2-strb.ll U test/CodeGen/Thumb2/ldr-str-imm12.ll U test/CodeGen/Thumb2/thumb2-strh.ll U test/CodeGen/Thumb2/thumb2-ldr.ll U test/CodeGen/Thumb2/thumb2-str_pre.ll U test/CodeGen/Thumb2/thumb2-str.ll U test/CodeGen/Thumb2/thumb2-ldrh.ll U utils/TableGen/TableGen.cpp U utils/TableGen/DisassemblerEmitter.cpp D utils/TableGen/RISCDisassemblerEmitter.h D utils/TableGen/RISCDisassemblerEmitter.cpp U Makefile.rules U lib/Target/ARM/ARMInstrNEON.td U lib/Target/ARM/Makefile U lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/AsmPrinter/ARMInstPrinter.h D lib/Target/ARM/Disassembler U lib/Target/ARM/ARMInstrFormats.td U lib/Target/ARM/ARMAddressingModes.h U lib/Target/ARM/Thumb2ITBlockPass.cpp llvm-svn: 98640
* Initial ARM/Thumb disassembler check-in. It consists of a tablgen backendJohnny Chen2010-03-161-0/+513
(RISCDisassemblerEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm instructions to help disassembly. We also changed the output of the addressing modes to omit the '+' from the assembler syntax #+/-<imm> or +/-<Rm>. See, for example, A8.6.57/58/60. And modified test cases to not expect '+' in +reg or #+num. For example, ; CHECK: ldr.w r9, [r7, #28] llvm-svn: 98637
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