summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
diff options
context:
space:
mode:
authorBob Wilson <bob.wilson@apple.com>2010-08-11 23:10:46 +0000
committerBob Wilson <bob.wilson@apple.com>2010-08-11 23:10:46 +0000
commitadd513112a6bca3bcffbf460f41298d61c2bb676 (patch)
treefba977b10bb25613c36e59a42b112b2b4e1caf10 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
parent9c473e46f3846c8678d1d79911a8eb40e1c55bda (diff)
downloadbcm5719-llvm-add513112a6bca3bcffbf460f41298d61c2bb676.tar.gz
bcm5719-llvm-add513112a6bca3bcffbf460f41298d61c2bb676.zip
Move the ARM SSAT and USAT optional shift amount operand out of the
instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
-rw-r--r--llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 4de697e8bf6..f9eecb8acb2 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -106,7 +106,7 @@ static unsigned decodeARMInstruction(uint32_t &insn) {
// Ditto for STRT, which is a super-instruction for A8.6.210 Encoding A1 & A2.
// As a result, the decoder fails to deocode SSAT properly.
if (slice(insn, 27, 21) == 0x35 && slice(insn, 5, 4) == 1)
- return slice(insn, 6, 6) == 0 ? ARM::SSATlsl : ARM::SSATasr;
+ return ARM::SSAT;
// Ditto for RSCrs, which is a super-instruction for A8.6.146 & A8.6.147.
// As a result, the decoder fails to decode STRHT/LDRHT/LDRSHT/LDRSBT.
OpenPOWER on IntegriCloud