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* Formatting changes. No functionality change.Bill Wendling2011-01-031-80/+77
| | | | llvm-svn: 122789
* Use a StringSwitch<> instead of a manually constructed string matcher.Jim Grosbach2010-12-241-10/+7
| | | | llvm-svn: 122530
* Recognize a few more documented register name aliases for ARM in the asm lexer.Jim Grosbach2010-12-231-0/+18
| | | | llvm-svn: 122523
* Trailing whitespace.Jim Grosbach2010-12-221-15/+15
| | | | llvm-svn: 122456
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-13/+17
| | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. llvm-svn: 121747
* Fix the leak from r121401 of the Operands erased in the list but not deleted.Kevin Enderby2010-12-101-6/+15
| | | | llvm-svn: 121450
* Add support for parsing ARM arithmetic instructions that update or don't updateKevin Enderby2010-12-091-6/+45
| | | | | | | | | the condition codes. Where the ones that do have an 's' suffix and the ones that don't don't have the suffix. The trick is if MatchInstructionImpl() fails we try again after adding a CCOut operand with the correct value and removing the 's' if present. Four simple test cases added for now, lots more to come. llvm-svn: 121401
* Add parens to pacify gcc.Benjamin Kramer2010-12-071-1/+1
| | | | llvm-svn: 121142
* Encode the register operand of ARM CondCode operands correctly. ARM::CPSR ifJim Grosbach2010-12-061-2/+2
| | | | | | the instruction is predicated, reg0 otherwise. llvm-svn: 121020
* The ARM AsmMatcher needs to know that the CCOut operand is a register value,Jim Grosbach2010-12-061-1/+20
| | | | | | not an immediate. It stores either ARM::CPSR or reg0. llvm-svn: 121018
* * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same asBill Wendling2010-11-301-1/+1
| | | | | | | | | | t_addrmode_s4, but with a different scaling factor. * Encode the Thumb1 load and store instructions. This involved a bit of refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and were removed. llvm-svn: 120482
* Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almostBill Wendling2010-11-301-6/+35
| | | | | | | | | | certainly be made more generic. But it does allow us to parse something like: ldr r3, [r2, r4] correctly in Thumb mode. llvm-svn: 120408
* Add a few missing initializers.Jim Grosbach2010-11-291-2/+2
| | | | llvm-svn: 120350
* Nuke trailing whitespace.Jim Grosbach2010-11-291-3/+3
| | | | llvm-svn: 120344
* The "trap" instruction is one of this which doesn't have a condition code. HackBill Wendling2010-11-211-2/+5
| | | | | | the code to not add a "condition code" if it's trap. llvm-svn: 119937
* Use array_pod_sort because the list is contiguous.Bill Wendling2010-11-191-1/+1
| | | | llvm-svn: 119769
* Add support for parsing the writeback ("!") token.Bill Wendling2010-11-181-65/+80
| | | | llvm-svn: 119761
* Don't allocate the SmallVector of Registers. It gets messy figuring out whoBill Wendling2010-11-181-13/+5
| | | | | | | should delete what when the object gets copied around. It's also making valgrind upset. llvm-svn: 119747
* Proper encoding for VLDM and VSTM instructions. The register lists for theseBill Wendling2010-11-171-3/+27
| | | | | | | | | instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. llvm-svn: 119460
* Emit a '!' if this is a "writeback" register or memory address.Bill Wendling2010-11-101-2/+2
| | | | llvm-svn: 118662
* Rename a parameter to avoid confusion with a local variableMatt Beaumont-Gay2010-11-101-3/+3
| | | | llvm-svn: 118656
* Emit the warning about the register list not being in ascending order only once.Bill Wendling2010-11-091-5/+8
| | | | llvm-svn: 118653
* s/std::vector/SmallVector/Bill Wendling2010-11-091-12/+11
| | | | llvm-svn: 118648
* Delete the allocated vector.Bill Wendling2010-11-091-0/+4
| | | | llvm-svn: 118644
* Two types of instructions have register lists:Bill Wendling2010-11-091-56/+32
| | | | | | | | | | | * LDM, et al, uses a bit mask to indicate the register list. * VLDM, et al, uses a base register plus number. The LDM instructions may be non-contiguous, but the VLDM ones must be contiguous. Those are semantic checks that should be done later in the compiler. Also postpone the creation of the bit mask until it's needed. llvm-svn: 118640
* The "addRegListOperands()" function returns the start register and the totalBill Wendling2010-11-081-15/+21
| | | | | | number of registers in the list. llvm-svn: 118456
* Revert.Bill Wendling2010-11-081-1/+1
| | | | llvm-svn: 118389
* In this context, a reglist is a reg.Bill Wendling2010-11-071-1/+1
| | | | llvm-svn: 118375
* Add support for parsing register lists. We can't use a bitfield to keep track ofBill Wendling2010-11-061-22/+64
| | | | | | | | | | | the registers, because the register numbers may be much greater than the number of bits available in the machine's register. I extracted the register list verification code out of the actual parsing of the registers. This made checking for errors much easier. It also limits the number of warnings that would be emitted for cascading infractions. llvm-svn: 118363
* Return the base register of a register list for the "getReg()" method. This isBill Wendling2010-11-061-3/+8
| | | | | | | to satisfy the ClassifyOperand method of the Asm matcher without having to add a RegList type to every back-end. llvm-svn: 118360
* General cleanup:Bill Wendling2010-11-061-36/+21
| | | | | | | - Make ARMOperand a class so that some things are internal to the class. - Reformatting. llvm-svn: 118357
* Add a RegList (register list) object to ARMOperand. It will be used soon to holdBill Wendling2010-11-061-1/+38
| | | | | | | (surprise!) a list of registers. Register lists are consecutive, so we only need to record the start register plus the number of registers. llvm-svn: 118351
* Fix grammar.Bill Wendling2010-11-061-1/+1
| | | | llvm-svn: 118341
* Fix grammar.Bill Wendling2010-11-061-3/+3
| | | | llvm-svn: 118340
* MatchRegisterName() returns 0 if it can't match the register.Bill Wendling2010-11-061-2/+2
| | | | llvm-svn: 118339
* Use TryParseRegister() instead of MatchRegisterName(). The former returns -1Bill Wendling2010-11-061-5/+2
| | | | | | while the latter doesn't. llvm-svn: 118338
* Hook up the '.code {16|32}' directive to the streamer.Jim Grosbach2010-11-051-2/+5
| | | | llvm-svn: 118310
* Hook up the '.thumb_func' directive to the streamer.Jim Grosbach2010-11-051-3/+5
| | | | llvm-svn: 118307
* Fix past-o.Jim Grosbach2010-11-051-1/+1
| | | | llvm-svn: 118304
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-031-3/+13
| | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
* Add FIXME.Jim Grosbach2010-11-011-0/+1
| | | | llvm-svn: 117936
* Mark ARM subtarget features that are available for the assembler.Jim Grosbach2010-11-011-1/+5
| | | | llvm-svn: 117929
* trailing whitespaceJim Grosbach2010-11-011-5/+5
| | | | llvm-svn: 117927
* Tidy up.Jim Grosbach2010-10-301-1/+1
| | | | llvm-svn: 117782
* simplify this code.Chris Lattner2010-10-301-8/+4
| | | | llvm-svn: 117771
* split MaybeParseRegister into its two logical uses, eliminating malloc+free ↵Chris Lattner2010-10-301-35/+38
| | | | | | traffic. llvm-svn: 117769
* Some instructions end with an "ls" prefix, but it doesn't indicate that they areBill Wendling2010-10-291-3/+9
| | | | | | conditional. Check for those instructions explicitly. llvm-svn: 117747
* add FIXMEJim Grosbach2010-10-291-0/+5
| | | | llvm-svn: 117718
* Handle ARM addrmode5 instructions with an offset.Jim Grosbach2010-10-291-9/+24
| | | | llvm-svn: 117672
* Revert 117660. Apparently it's not as trivial as that...Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117663
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