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path: root/llvm/lib/Target/ARM/ARMSubtarget.h
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* Move function dependent resetting of a subtarget variable out of theEric Christopher2014-07-041-11/+2
| | | | | | | | | | subtarget. This involved having the movt predicate take the current function - since we care about size in instruction selection for whether or not to use movw/movt take the function so we can check the attributes. This required adding the current MachineFunction to FastISel and propagating through. llvm-svn: 212309
* Move all of the ARM subtarget features down onto the subtargetEric Christopher2014-06-261-1/+21
| | | | | | rather than the target machine. llvm-svn: 211799
* Add a new subtarget hook for whether or not we'd like to enableEric Christopher2014-06-191-0/+3
| | | | | | | | | the atomic load linked expander pass to run for a particular subtarget. This requires a check of the subtarget and so save the TargetMachine rather than only TargetLoweringInfo and update all callers. llvm-svn: 211314
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-181-0/+3
| | | | | | | | | This required untangling a mess of headers that included around. This a recommit of r210953 with a fix for the removed accessor for JITInfo. llvm-svn: 211233
* Temporarily revert r210953 in an attempt to bring the ARM buildbotsEric Christopher2014-06-151-3/+0
| | | | | | back. llvm-svn: 210996
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-131-0/+3
| | | | | | This required untangling a mess of headers that included around. llvm-svn: 210953
* Move ARMSelectionDAGInfo from the TargetMachine to the subtarget.Eric Christopher2014-06-131-0/+3
| | | | llvm-svn: 210862
* Move to a private function to initialize subtarget dependenciesEric Christopher2014-06-131-0/+10
| | | | | | | | so we can use initializer lists for the ARMSubtarget and then use this to initialize a moved DataLayout on the subtarget from the TargetMachine. llvm-svn: 210861
* CodeGen: enable mov.w/mov.t pairs with minsize for WoASaleem Abdulrasool2014-06-121-1/+6
| | | | | | | | | Windows on ARM uses COFF/PE which is intrinsically position independent. For the case of 32-bit immediates, use a pair-wise relocation as otherwise we may exceed the range of operators. This fixes a code generation crash when using -Oz when targeting Windows on ARM. llvm-svn: 210814
* Add a subtarget hook: enablePostMachineScheduler.Andrew Trick2014-06-041-0/+3
| | | | | | | | | | | | | | | As requested by AArch64 subtargets. Note that this will have no effect until the AArch64 target actually enables the pass like this: substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); As soon as armv7 switches over, PostMachineScheduler will become the default postRA scheduler, so this won't be necessary any more. Targets using the old postRA schedule would then do: substitutePass(&PostMachineSchedulerID, &PostRASchedulerID); llvm-svn: 210167
* Re-enable inline memcpy expansion for Thumb1.James Molloy2014-05-161-3/+1
| | | | | | Patch by Moritz Roth! llvm-svn: 208994
* Tidy up. Trailing whitespace.Jim Grosbach2014-04-031-2/+2
| | | | llvm-svn: 205583
* ARM: update subtarget information for Windows on ARMSaleem Abdulrasool2014-04-021-8/+10
| | | | | | | Update the subtarget information for Windows on ARM. This enables using the MC layer to target Windows on ARM. llvm-svn: 205459
* ARM: Add support for segmented stacksOliver Stannard2014-04-021-0/+3
| | | | | | Patch by Alex Crichton, ILyoan, Luqman Aden and Svetoslav. llvm-svn: 205430
* ARM: teach LLVM that Cortex-A7 is very similar to A8.Tim Northover2014-04-011-0/+1
| | | | llvm-svn: 205314
* ARM: add cyclone CPU with ZeroCycleZeroing feature.Tim Northover2014-04-011-0/+5
| | | | | | | | The Cyclone CPU is similar to swift for most LLVM purposes, but does have two preferred instructions for zeroing a VFP register. This teaches LLVM about them. llvm-svn: 205309
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-281-1/+7
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 llvm-svn: 205007
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-2/+2
| | | | | | class. llvm-svn: 203433
* Unaligned access is supported on ARMv6 and ARMv7 for the NetBSD target.Joerg Sonnenberger2014-02-021-0/+3
| | | | | | Patch from Matt Thomas. llvm-svn: 200654
* Reenable ARM EHABI on Android.Evgeniy Stepanov2014-01-301-1/+2
| | | | | | Broken in r200388. llvm-svn: 200466
* Enable EHABI by defaultRenato Golin2014-01-291-0/+10
| | | | | | | | | | | | | | | | | | | | | | After all hard work to implement the EHABI and with the test-suite passing, it's time to turn it on by default and allow users to disable it as a work-around while we fix the eventual bugs that show up. This commit also remove the -arm-enable-ehabi-descriptors, since we want the tables to be printed every time the EHABI is turned on for non-Darwin ARM targets. Although MCJIT EHABI is not working yet (needs linking with the right libraries), this commit also fixes some relocations on MCJIT regarding the EH tables/lib calls, and update some tests to avoid using EH tables when none are needed. The EH tests in the test-suite that were previously disabled on ARM now pass with these changes, so a follow-up commit on the test-suite will re-enable them. llvm-svn: 200388
* ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks.Tim Northover2014-01-061-0/+3
| | | | | | | | | | | | | | | | | | The ARM backend has been using most of the MachO related subtarget checks almost interchangeably, and since the only target it's had to run on has been IOS (which is all three of MachO, Darwin and IOS) it's worked out OK so far. But we'd like to support embedded targets under the "*-*-none-macho" triple, which means everything starts falling apart and inconsistent behaviours emerge. This patch should pick a reasonably sensible set of behaviours for the new triple (and any others that come along, with luck). Some choices were debatable (notably FP == r7 or r11), but we can revisit those later when deficiencies become apparent. llvm-svn: 198617
* ARM: keep special non-AEABIness of "-darwin-eabi" triples for nowTim Northover2014-01-061-2/+5
| | | | | | | | | | Longer term, we want to move users to "*-*-*-macho" for embedded work, but for now people are relying on the last thing we told them, which is unfortunately "*-*-darwin-eabi". rdar://problem/15703934 llvm-svn: 198602
* Make the ARM ABI selectable via SubtargetFeature.Rafael Espindola2014-01-021-2/+9
| | | | | | | This patch makes it possible to select the ABI with -mattr. It will be used to forward clang's -target-abi option to llvm's CodeGen. llvm-svn: 198304
* ARM: set default float ABI based on triple.Tim Northover2013-12-181-0/+5
| | | | | | | | | | | | Clang sets the float-abi target option manually, but no longer annotates each function with its ABI. This can lead to confusing mistmatch between "clang -emit-llvm | llc" and normal clang invocations. Besides which, gnueabihf actually *is* hard-float. Defaulting to soft was just perverse. llvm-svn: 197554
* Recognize EABIHF as environment and use it for RTAPI + VFP.Joerg Sonnenberger2013-12-161-1/+2
| | | | llvm-svn: 197405
* Make Triple's isOSBinFormatXXX functions partition triple-space.Tim Northover2013-12-101-1/+1
| | | | | | | | | | | Most users would be surprised if "isCOFF" and "isMachO" were simultaneously true, unless they'd put the compiler in a box with a gun attached to a photon detector. This makes sure precisely one of the three formats is true for any triple and simplifies some target logic based on that. llvm-svn: 196934
* Added support for mcpu kraitAna Pazos2013-12-061-2/+3
| | | | | | | | | | | | - krait processor currently modeled with the same features as A9. - Krait processor additionally has VFP4 (fused multiply add/sub) and hardware division features enabled. - krait has currently the same Schedule model as A9 - krait cpu flag is not recognized by the GNU assembler yet, it is replaced with march=armv7-a to avoid a lower march from being used. llvm-svn: 196619
* ARM: decide whether to use movw/movt based on "minsize" attribute.Tim Northover2013-12-021-1/+6
| | | | llvm-svn: 196102
* Add support for Cortex-A12.Richard Barton2013-11-221-2/+2
| | | | | | Patch by Oliver Stannard! llvm-svn: 195448
* [ARM] add basic Cortex-A7 support to LLVM backendArtyom Skrobov2013-11-211-1/+2
| | | | llvm-svn: 195358
* Enable generating legacy IT block for AArch32Weiming Zhao2013-11-131-0/+6
| | | | | | | | | | | | | | By default, the behavior of IT block generation will be determinated dynamically base on the arch (armv8 vs armv7). This patch adds backend options: -arm-restrict-it and -arm-no-restrict-it. The former one restricts the generation of IT blocks (the same behavior as thumbv8) for both arches. The later one allows the generation of legacy IT block (the same behavior as ARMv7 Thumb2) for both arches. Clang will support -mrestrict-it and -mno-restrict-it, which is compatible with GCC. llvm-svn: 194592
* Enable optimization of sin / cos pair into call to __sincos_stret for iOS7+.Bob Wilson2013-11-031-0/+4
| | | | | | | rdar://12856873 Patch by Evan Cheng, with a fix for rdar://13209539 by Tilmann Scheller llvm-svn: 193942
* [ARM] Add Virtualization subtarget feature and more build attributes in this ↵Bradley Smith2013-11-011-0/+5
| | | | | | | | | | | | | | | area Add a Virtualization ARM subtarget feature along with adding proper build attribute emission for Tag_Virtualization_use (encodes Virtualization and TrustZone) and Tag_MPextension_use. Also rework test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll testcase to something that is more maintainable. This changes the focus of this testcase away from testing CPU defaults (which is tested elsewhere), onto specifically testing that attributes are encoded correctly. llvm-svn: 193859
* ARM: Add subtarget feature for CRCBernard Ogden2013-10-291-0/+4
| | | | | | | | Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend. Differential Revision: http://llvm-reviews.chandlerc.com/D2036 llvm-svn: 193599
* ARM: don't expand atomicrmw inline on Cortex-M0Tim Northover2013-10-251-0/+3
| | | | | | | | | | There's a barrier instruction so that should still be used, but most actual atomic operations are going to need a platform decision on the correct behaviour (either nop if single-threaded or OS-support otherwise). rdar://problem/15287210 llvm-svn: 193399
* Add Cortex-A57 supportBernard Ogden2013-10-141-1/+1
| | | | llvm-svn: 192591
* Add subtarget feature support for Cortex-A53Bernard Ogden2013-10-141-1/+1
| | | | | | | Some previous implicit defaults have changed, for example FP and NEON are now on by default. llvm-svn: 192590
* [ARM] Improve build attributes emission.Amara Emerson2013-10-071-0/+1
| | | | llvm-svn: 192111
* ARM: allow cortex-m0 to use hint instructionsTim Northover2013-10-071-1/+2
| | | | | | | | | | | The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 llvm-svn: 192097
* [ARM] Split A/R class into separate subtarget features.Amara Emerson2013-09-231-6/+9
| | | | | | Patch by Bradley Smith. llvm-svn: 191202
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-191-0/+4
| | | | llvm-svn: 190996
* [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line optionsJoey Gouly2013-09-131-3/+3
| | | | | | to be more consistent. llvm-svn: 190692
* Clean up some usage of Triple. The base class has methods for determining ↵Cameron Esfahani2013-08-291-3/+3
| | | | | | if the target is iOS and Linux. llvm-svn: 189604
* ARM EABI divmod supportRenato Golin2013-07-161-0/+8
| | | | | | | | | | | | This patch enables calls to __aeabi_idivmod when in EABI mode, by using the remainder value returned on registers (R1), enabled by the ARM triple "none-eabi". Note that Darwin and GNUEABI triples will continue lowering on GNU style, that is, using the stack for the remainder. Still need to add SREM/UREM support fix for 64-bit lowering. llvm-svn: 186390
* Remove unused memberDavid Blaikie2013-06-281-4/+0
| | | | llvm-svn: 185219
* Add a Subtarget feature 'v8fp' to the ARM backend.Joey Gouly2013-06-271-1/+3
| | | | llvm-svn: 185073
* Add a subtarget feature 'v8' to the ARM backend.Joey Gouly2013-06-261-1/+4
| | | | | | This allows for targeting the ARMv8 AArch32 variant. llvm-svn: 184967
* ARM: Add Performance Monitor Extensions featureTim Northover2013-05-231-0/+6
| | | | | | | | | | Performance monitors, including a basic cycle counter, are an official extension in the ARMv7 specification. This adds support for enabling and disabling them, orthogonally from CPU selection. rdar://problem/13939186 llvm-svn: 182602
* Support unaligned load/store on more ARM targetsJF Bastien2013-05-171-3/+2
| | | | | | | | | | | | | | | | | | | | | This patch matches GCC behavior: the code used to only allow unaligned load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for v6+ Darwin as well as for v7+ on Linux and NaCl. The distinction is made because v6 doesn't guarantee support (but LLVM assumes that Apple controls hardware+kernel and therefore have conformant v6 CPUs), whereas v7 does provide this guarantee (and Linux/NaCl behave sanely). The patch keeps the -arm-strict-align command line option, and adds -arm-no-strict-align. They behave similarly to GCC's -mstrict-align and -mnostrict-align. I originally encountered this discrepancy in FastIsel tests which expect unaligned load/store generation. Overall this should slightly improve performance in most cases because of reduced I$ pressure. llvm-svn: 182175
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