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path: root/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
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* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-0/+1
| | | | llvm-svn: 75036
* Push methods into base class in preparation for sharing.David Goodwin2009-07-081-533/+1
| | | | llvm-svn: 75020
* Start converting to new error handling API.Torok Edwin2009-07-081-2/+2
| | | | | | | cerr+abort -> llvm_report_error assert(0)+abort -> LLVM_UNREACHABLE (assert(0)+llvm_unreachable-> abort() included) llvm-svn: 75018
* Start breaking out common base functionality for register info.David Goodwin2009-07-081-830/+0
| | | | llvm-svn: 75016
* Fix a comment typo.Bob Wilson2009-07-011-1/+1
| | | | llvm-svn: 74650
* Simplify a bitAnton Korobeynikov2009-06-271-37/+23
| | | | llvm-svn: 74385
* ARM refactoring. Step 2: split RegisterInfoAnton Korobeynikov2009-06-271-615/+144
| | | | llvm-svn: 74384
* For Darwin on ARMv6 and newer, make register r9 available for use as aBob Wilson2009-06-221-2/+31
| | | | | | caller-saved register. llvm-svn: 73901
* hasFP should return true if frame address is taken.Evan Cheng2009-06-221-1/+3
| | | | llvm-svn: 73893
* Remove UseThumbBacktraces. Just check if subtarget is darwin.Evan Cheng2009-06-181-4/+3
| | | | llvm-svn: 73734
* - Update register allocation hint after coalescing. This is done by the ↵Evan Cheng2009-06-181-63/+95
| | | | | | | | | target since the hint is target dependent. This is important for ARM register pair hints. - Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping. - More fixes to get ARM load / store double word working. llvm-svn: 73671
* On Darwin, frame pointer r7 is never available.Evan Cheng2009-06-151-2/+2
| | | | llvm-svn: 73434
* Part 1.Evan Cheng2009-06-151-4/+301
| | | | | | | | | | | | | | | | | | | | | - Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent. - Allow targets to specify alternative register allocation orders based on allocation hint. Part 2. - Use the register allocation hint system to implement more aggressive load / store multiple formation. - Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g. v1025 = LDR v1024, 0 v1026 = LDR v1024, 0 => v1025,v1026 = LDRD v1024, 0 If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair. - Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions. This is work in progress, not yet enabled. llvm-svn: 73381
* Untabification.Bill Wendling2009-05-301-1/+1
| | | | llvm-svn: 72604
* Follow up on new support for memory operands in ARM inline assembly.Bob Wilson2009-05-191-0/+4
| | | | | | This fixes pr4233. llvm-svn: 72115
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-131-15/+15
| | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). llvm-svn: 71722
* PR2985 / <rdar://problem/6584986>Jim Grosbach2009-04-071-9/+36
| | | | | | | | | | When compiling in Thumb mode, only the low (R0-R7) registers are available for most instructions. Breaking the low registers into a new register class handles this. Uses of R12, SP, etc, are handled explicitly where needed with copies inserted to move results into low registers where the rest of the code generator can deal with them. llvm-svn: 68545
* Fix some significant problems with constant pools that resulted in ↵Evan Cheng2009-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. llvm-svn: 66875
* Propagate debug loc info through prologue/epilogue.Bill Wendling2009-02-231-4/+8
| | | | llvm-svn: 65298
* and one more fileDale Johannesen2009-02-131-64/+92
| | | | llvm-svn: 64430
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-0/+4
| | | | llvm-svn: 63938
* Preliminary ARM debug support based on patch by Mikael of FlexyCore.Evan Cheng2008-12-101-2/+1
| | | | llvm-svn: 60851
* Add a sanity-check to tablegen to catch the case where isSimpleLoadDan Gohman2008-12-031-1/+1
| | | | | | | | | is set but mayLoad is not set. Fix all the problems this turned up. Change code to not use isSimpleLoad instead of mayLoad unless it really wants isSimpleLoad. llvm-svn: 60459
* Fix encoding of single-precision VFP registers.Evan Cheng2008-11-121-0/+74
| | | | llvm-svn: 59102
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-4/+4
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Re-apply 56683 with fixes.Evan Cheng2008-09-271-1/+2
| | | | llvm-svn: 56748
* Temporarily reverting r56683. This is causing a failure during the build of ↵Bill Wendling2008-09-261-3/+1
| | | | | | | | | | | | | | | | | llvm-gcc: /Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311. ../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://developer.apple.com/bugreporter> for instructions. {standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb" {standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression {standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb" ... llvm-svn: 56703
* Fix @llvm.frameaddress codegen. FP elimination optimization should be ↵Evan Cheng2008-09-261-1/+3
| | | | | | disabled when frame address is desired. Also add support for depth > 0. llvm-svn: 56683
* Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray2008-04-161-1/+1
| | | | | | instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-311-30/+12
| | | | llvm-svn: 48995
* Spiller now remove unused spill slots.Evan Cheng2008-02-271-0/+2
| | | | llvm-svn: 47657
* Remove bunch of gcc 4.3-related warnings from TargetAnton Korobeynikov2008-02-201-1/+2
| | | | llvm-svn: 47369
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
| | | | llvm-svn: 46930
* rename MachineInstr::setInstrDescriptor -> setDescChris Lattner2008-01-111-7/+7
| | | | llvm-svn: 45871
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-2/+2
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-2/+2
| | | | | | | | | | | | | | | that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-151/+45
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-2/+2
| | | | llvm-svn: 45667
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45656
* Move some more functionality from MRegisterInfo to TargetInstrInfo.Owen Anderson2008-01-041-44/+0
| | | | llvm-svn: 45603
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-128/+0
| | | | llvm-svn: 45484
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-28/+0
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-11/+12
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-2/+2
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-8/+8
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* use simplified operand addition methods.Chris Lattner2007-12-301-8/+9
| | | | llvm-svn: 45437
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+1
| | | | llvm-svn: 45418
* DohEvan Cheng2007-12-081-1/+1
| | | | llvm-svn: 44694
* Fix a compilation warning.Evan Cheng2007-12-081-1/+1
| | | | llvm-svn: 44692
* Add a argument to storeRegToStackSlot and storeRegToAddr to specify whetherEvan Cheng2007-12-051-7/+41
| | | | | | the stored register is killed. llvm-svn: 44600
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