rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.

llvm-svn: 45667

1 files changed, 2 insertions, 2 deletions

diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
index ea775f74a12..316026234e7 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -690,7 +690,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   }
 
   unsigned Opcode = MI.getOpcode();
-  const TargetInstrDescriptor &Desc = TII.get(Opcode);
+  const TargetInstrDescriptor &Desc = *MI.getInstrDescriptor();
   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
   bool isSub = false;
 
@@ -885,7 +885,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   assert(Offset && "This code isn't needed if offset already handled!");
 
   if (isThumb) {
-    if (TII.isLoad(Opcode)) {
+    if (Desc.isSimpleLoad()) {
       // Use the destination register to materialize sp + offset.
       unsigned TmpReg = MI.getOperand(0).getReg();
       bool UseRR = false;