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* PR2985 / <rdar://problem/6584986>Jim Grosbach2009-04-071-9/+36
| | | | | | | | | | When compiling in Thumb mode, only the low (R0-R7) registers are available for most instructions. Breaking the low registers into a new register class handles this. Uses of R12, SP, etc, are handled explicitly where needed with copies inserted to move results into low registers where the rest of the code generator can deal with them. llvm-svn: 68545
* Fix some significant problems with constant pools that resulted in ↵Evan Cheng2009-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. llvm-svn: 66875
* Propagate debug loc info through prologue/epilogue.Bill Wendling2009-02-231-4/+8
| | | | llvm-svn: 65298
* and one more fileDale Johannesen2009-02-131-64/+92
| | | | llvm-svn: 64430
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-0/+4
| | | | llvm-svn: 63938
* Preliminary ARM debug support based on patch by Mikael of FlexyCore.Evan Cheng2008-12-101-2/+1
| | | | llvm-svn: 60851
* Add a sanity-check to tablegen to catch the case where isSimpleLoadDan Gohman2008-12-031-1/+1
| | | | | | | | | is set but mayLoad is not set. Fix all the problems this turned up. Change code to not use isSimpleLoad instead of mayLoad unless it really wants isSimpleLoad. llvm-svn: 60459
* Fix encoding of single-precision VFP registers.Evan Cheng2008-11-121-0/+74
| | | | llvm-svn: 59102
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-4/+4
| | | | | | isReg, etc., from isRegister, etc. llvm-svn: 57006
* Re-apply 56683 with fixes.Evan Cheng2008-09-271-1/+2
| | | | llvm-svn: 56748
* Temporarily reverting r56683. This is causing a failure during the build of ↵Bill Wendling2008-09-261-3/+1
| | | | | | | | | | | | | | | | | llvm-gcc: /Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311. ../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap Please submit a full bug report, with preprocessed source if appropriate. See <URL:http://developer.apple.com/bugreporter> for instructions. {standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb" {standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression {standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb" ... llvm-svn: 56703
* Fix @llvm.frameaddress codegen. FP elimination optimization should be ↵Evan Cheng2008-09-261-1/+3
| | | | | | disabled when frame address is desired. Also add support for depth > 0. llvm-svn: 56683
* Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray2008-04-161-1/+1
| | | | | | instruction. X86, PowerPC and ARM are implemented llvm-svn: 49809
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-311-30/+12
| | | | llvm-svn: 48995
* Spiller now remove unused spill slots.Evan Cheng2008-02-271-0/+2
| | | | llvm-svn: 47657
* Remove bunch of gcc 4.3-related warnings from TargetAnton Korobeynikov2008-02-201-1/+2
| | | | llvm-svn: 47369
* Rename MRegisterInfo to TargetRegisterInfo.Dan Gohman2008-02-101-1/+1
| | | | llvm-svn: 46930
* rename MachineInstr::setInstrDescriptor -> setDescChris Lattner2008-01-111-7/+7
| | | | llvm-svn: 45871
* rename TargetInstrDescriptor -> TargetInstrDesc.Chris Lattner2008-01-071-2/+2
| | | | | | | Make MachineInstr::getDesc return a reference instead of a pointer, since it can never be null. llvm-svn: 45695
* Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflectsChris Lattner2008-01-071-2/+2
| | | | | | | | | | | | | | | that it is cheap and efficient to get. Move a variety of predicates from TargetInstrInfo into TargetInstrDescriptor, which makes it much easier to query a predicate when you don't have TII around. Now you can use MI->getDesc()->isBranch() instead of going through TII, and this is much more efficient anyway. Not all of the predicates have been moved over yet. Update old code that used MI->getInstrDescriptor()->Flags to use the new predicates in many places. llvm-svn: 45674
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-151/+45
| | | | | | Some day I'll get it all moved over... llvm-svn: 45672
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-2/+2
| | | | llvm-svn: 45667
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | llvm-svn: 45656
* Move some more functionality from MRegisterInfo to TargetInstrInfo.Owen Anderson2008-01-041-44/+0
| | | | llvm-svn: 45603
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-128/+0
| | | | llvm-svn: 45484
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-28/+0
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-11/+12
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-2/+2
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-8/+8
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* use simplified operand addition methods.Chris Lattner2007-12-301-8/+9
| | | | llvm-svn: 45437
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+1
| | | | llvm-svn: 45418
* DohEvan Cheng2007-12-081-1/+1
| | | | llvm-svn: 44694
* Fix a compilation warning.Evan Cheng2007-12-081-1/+1
| | | | llvm-svn: 44692
* Add a argument to storeRegToStackSlot and storeRegToAddr to specify whetherEvan Cheng2007-12-051-7/+41
| | | | | | the stored register is killed. llvm-svn: 44600
* Remove redundant foldMemoryOperand variants and other code clean up.Evan Cheng2007-12-021-1/+5
| | | | llvm-svn: 44517
* Add parameter to getDwarfRegNum to permit targetsDale Johannesen2007-11-131-1/+1
| | | | | | | | to use different mappings for EH and debug info; no functional change yet. Fix warning in X86CodeEmitter. llvm-svn: 44056
* Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stackBill Wendling2007-11-131-1/+4
| | | | | | | | | | | adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If not, then there is the potential for the stack to be changed while the stack's being used by another instruction (like a call). This can only result in tears... llvm-svn: 44037
* Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov2007-11-111-0/+5
| | | | | | | | This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, llvm-svn: 43997
* - Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but ↵Evan Cheng2007-10-181-2/+2
| | | | | | | | only returns the opcode of the instruction post unfolding. - Fix some copy+paste bugs. llvm-svn: 43153
* Use SmallVectorImpl instead of SmallVector with hardcoded size in MRegister ↵Evan Cheng2007-10-181-4/+4
| | | | | | public interface. llvm-svn: 43150
* - Added a few target hooks to generate load / store instructions from / to anyEvan Cheng2007-10-051-21/+110
| | | | | | | | address (not just from / to frameindexes). - Added target hooks to unfold load / store instructions / SDNodes into separate load, data processing, store instructions / SDNodes. llvm-svn: 42621
* Allow copyRegToReg to emit cross register classes copies.Evan Cheng2007-09-261-4/+10
| | | | | | Tested with "make check"! llvm-svn: 42346
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-2/+2
| | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; llvm-svn: 40033
* Only adjust esp around calls in presence of alloca.Evan Cheng2007-07-191-1/+1
| | | | llvm-svn: 40030
* Long live the exception handling!Anton Korobeynikov2007-07-141-2/+3
| | | | | | | | | | | | | | | This patch fills the last necessary bits to enable exceptions handling in LLVM. Currently only on x86-32/linux. In fact, this patch adds necessary intrinsics (and their lowering) which represent really weird target-specific gcc builtins used inside unwinder. After corresponding llvm-gcc patch will land (easy) exceptions should be more or less workable. However, exceptions handling support should not be thought as 'finished': I expect many small and not so small glitches everywhere. llvm-svn: 39855
* Remove clobbersPred. Add an OptionalDefOperand to instructions which have ↵Evan Cheng2007-07-101-5/+9
| | | | | | the 's' bit. llvm-svn: 38501
* Added ARM::CPSR to represent ARM CPSR status register.Evan Cheng2007-07-051-49/+59
| | | | llvm-svn: 37894
* Add missing const qualifiers.Evan Cheng2007-05-291-3/+3
| | | | llvm-svn: 37342
* Add PredicateOperand to all ARM instructions that have the condition field.Evan Cheng2007-05-151-48/+77
| | | | llvm-svn: 37066
* Fix PR1390 in a better way.Lauro Ramos Venancio2007-05-071-12/+41
| | | | llvm-svn: 36916
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