summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-1/+1
| | | | | | | | | | | | | The getPointerRegClass() hook can return register classes that depend on the calling convention of the current function (ptr_rc_tailcall). So far, we have been able to infer the calling convention from the subtarget alone, but as we add support for multiple calling conventions per target, that no longer works. Patch by Yiannis Tsiouris! llvm-svn: 156328
* ARM: Nuke remnant bogus code.Jim Grosbach2012-04-241-2/+0
| | | | | | | | r154362 was supposed to delete this bit, but obviously didn't. rdar://11305594 llvm-svn: 155465
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-1/+1
| | | | | | since they are equivalent. llvm-svn: 155188
* ARM LDR/LDRT has the same encoding collision as STR/STRT.Jim Grosbach2012-04-101-8/+7
| | | | | | Generalized logic of r154141. llvm-svn: 154362
* ARM: Don't form a t2LDRi8 or t2STRi8 with an offset of zero.Jim Grosbach2012-04-051-0/+8
| | | | | | | | | | | | | | | | | The load/store optimizer splits LDRD/STRD into two instructions when the register pairing doesn't work out. For negative offsets in Thumb2, it uses t2STRi8 to do that. That's fine, except for the case when the offset is in the range [-4,-1]. In that case, we'll also form a second t2STRi8 with the original offset plus 4, resulting in a t2STRi8 with a non-negative offset, which ends up as if it were an STRT, which is completely bogus. Similarly for loads. No testcase, unfortunately, as any I've been able to construct is both large and extremely fragile. rdar://11193937 llvm-svn: 154141
* Don't kill the base register when expanding strd.Jakob Stoklund Olesen2012-03-281-0/+4
| | | | | | | | | | | | | | When an strd instruction doesn't get the registers it wants, it can be expanded into two str instructions. Make sure the first str doesn't kill the base register in the case where the base and data registers are identical: t2STRi12 %R0<kill>, %R0, 4, pred:14, pred:%noreg t2STRi12 %R2<kill>, %R0, 8, pred:14, pred:%noreg <rdar://problem/11101911> llvm-svn: 153611
* Preserve implicit defs in ARMLoadStoreOptimizer.Jakob Stoklund Olesen2012-03-281-3/+20
| | | | | | | | | | | When a number of sub-register VLRDS instructions are combined into a VLDM, preserve any super-register implicit defs. This is required to keep the register scavenger and machine code verifier happy. Enable machine code verification after ARMLoadStoreOptimizer. ARM/2012-01-26-CopyPropKills.ll was failing because of this. llvm-svn: 153610
* Revert r153516: "Invalidate liveness in Thumb2ITBlockPass."Jakob Stoklund Olesen2012-03-281-4/+0
| | | | | | | | | | | | | | Revert r153519: "ARMLoadStoreOptimizer invalidates register liveness." These patches caused miscompilations in povray by turning off branch folding's updating of live-in lists. It turns out the the late scheduler depends on the live-in lists, even if it doesn't need correct kill flags. <rdar://problem/11139228> llvm-svn: 153593
* ARMLoadStoreOptimizer invalidates register liveness.Jakob Stoklund Olesen2012-03-271-0/+4
| | | | | | | | | | This pass tries to update kill flags, but there are still many bugs. Passes after the load/store optimizer don't need accurate liveness, so don't even try. <rdar://problem/11101911> llvm-svn: 153519
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-8/+8
| | | | llvm-svn: 153500
* Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper2012-03-261-1/+1
| | | | llvm-svn: 153422
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Do not fold ADD / SUB into load / store (to form pre-indexed, post-indexedEvan Cheng2012-02-071-24/+58
| | | | | | | | load / store) if the ADD / SUB has a live definition of CPSR. Bug reported by David Meyer. Alas, no test case. llvm-svn: 149970
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-24/+0
| | | | llvm-svn: 148578
* ARM Ld/St Optimizer fix.Andrew Trick2012-01-111-3/+4
| | | | | | | | Allow LDRD to be formed from pairs with different LDR encodings. This was the original intention of the pass. Somewhere along the way, the LDR opcodes were refined which broke the optimization. We really don't care what the original opcodes are as long as they both map to the same LDRD and the immediate still fits. Fixes rdar://10435045 ARMLoadStoreOptimization cannot handle mixed LDRi8/LDRi12 llvm-svn: 147922
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-7/+5
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build.NAKAMURA Takumi2011-11-251-0/+1
| | | | llvm-svn: 145129
* Preserve MachineMemOperands in ARMLoadStoreOptimizer.Andrew Trick2011-11-111-0/+22
| | | | | | Fixes PR8113. llvm-svn: 144409
* Hide cpu name checking in ARMSubtarget.Evan Cheng2011-11-091-1/+1
| | | | llvm-svn: 144154
* Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ↵Evan Cheng2011-11-081-3/+9
| | | | | | ldm or ldr pairs. llvm-svn: 144123
* Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand ↵Owen Anderson2011-08-291-1/+2
| | | | | | encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite. llvm-svn: 138766
* Update the load-store optimizer for changes to the operands on LDR_PRE_IMM ↵Owen Anderson2011-08-291-4/+10
| | | | | | and LDRB_PRE_IMM in r138653. llvm-svn: 138746
* invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We ↵Owen Anderson2011-08-261-1/+1
| | | | | | were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
* ARM STR_POST_IMM offset encoding fix in load/store optimizer.Jim Grosbach2011-08-121-13/+10
| | | | | | | | | Tidy up the code a bit and push the definition of the value next to the uses to try to minimize this sort of issue from arising again while I'm at it. rdar://9945172 llvm-svn: 137525
* ARM refactor indexed store instructions.Jim Grosbach2011-08-051-2/+8
| | | | | | | | | | Refactor STR[B] pre and post indexed instructions to use addressing modes for memory operands, which is necessary for assembly parsing and is more consistent with the rest of the memory instruction definitions. Make some incremental progress on refactoring away the mega-operand addrmode2 along the way, which is nice. llvm-svn: 136978
* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-261-3/+3
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+2
| | | | | | ARM MC code from target. llvm-svn: 135636
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-291-10/+2
| | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. llvm-svn: 134114
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-11/+11
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-1/+1
| | | | llvm-svn: 133944
* Clean up comment a bit.Eric Christopher2011-05-251-2/+2
| | | | llvm-svn: 132083
* Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing ↵Cameron Zwarich2011-05-181-4/+7
| | | | | | turned on. llvm-svn: 131578
* use the MachineInstrBuilder operator-> to simplify some code.Chris Lattner2011-04-291-1/+1
| | | | | | There are probably more instances of this floating around. llvm-svn: 130474
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-4/+4
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Clean up some code for clarity.Bob Wilson2011-04-051-5/+24
| | | | llvm-svn: 128953
* Check early if this is an unsupported opcode, so that we can avoid ↵Owen Anderson2011-03-291-0/+4
| | | | | | needlessly instantiating the base register in some cases. llvm-svn: 128481
* Add safety check that didn't show up in testing.Owen Anderson2011-03-291-0/+1
| | | | llvm-svn: 128467
* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't ↵Owen Anderson2011-03-291-17/+5
| | | | | | actually exist. llvm-svn: 128461
* Do not form thumb2 ldrd / strd if the offset is by multiple of 4. rdar://9133587Evan Cheng2011-03-151-9/+3
| | | | llvm-svn: 127683
* Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as ↵Jakob Stoklund Olesen2011-02-151-21/+15
| | | | | | | | | | | | | | | | | | | | | | | | | well. This is necessary to avoid a crash in certain tangled situations where a kill flag is first correctly moved to a merged instruction, and then needs to be moved again: STR %R0, a... STR %R0<kill>, b... First becomes: STR %R0, b... STM a, %R0<kill>, ... and then: STM a, %R0, ... STM b, %R0<kill>, ... We can now remove the kill flag from the merged STM when needed. 8960050. llvm-svn: 125591
* Move code for OffsetCompare struct closer to where it is used.Bob Wilson2011-02-071-11/+11
| | | | llvm-svn: 125009
* Fix a few more places that should use MBB::getLastNonDebugInstr().Jakob Stoklund Olesen2011-01-131-1/+1
| | | | llvm-svn: 123408
* Do not model all INLINEASM instructions as having unmodelled side effects.Evan Cheng2011-01-071-1/+1
| | | | | | | | | | Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. llvm-svn: 123044
* PR8921: LDM/POP do not support interworking prior to v5t.Bob Wilson2011-01-061-1/+2
| | | | llvm-svn: 122970
* Missed the _RET versions of LDMIA.Bill Wendling2010-11-181-0/+2
| | | | llvm-svn: 119726
* Add missing opcodes now that this function's used in more than one place.Bill Wendling2010-11-171-0/+20
| | | | llvm-svn: 119539
* Revert r119109 for now. It's breaking 176.gcc.Evan Cheng2010-11-171-17/+0
| | | | llvm-svn: 119492
* The machine instruction no longer encodes the submode as a separate operand. WeBill Wendling2010-11-171-2/+8
| | | | | | should get the submode from the load/store multiple instruction's opcode. llvm-svn: 119461
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-67/+236
| | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> llvm-svn: 119310
* Make sure ARM multi load / store pass copies memoperands when forming ldrd / ↵Evan Cheng2010-11-151-0/+17
| | | | | | strd. pr8113. llvm-svn: 119109
OpenPOWER on IntegriCloud