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* ARM: fix more cases where predication may or may not be allowedTim Northover2013-06-261-2/+3
| | | | | | | | | | Unfortunately this addresses two issues (by the time I'd disentangled the logic it wasn't worth putting it back to half-broken): + Coprocessor instructions should all be predicable in Thumb mode. + BKPT should never be predicable. llvm-svn: 184965
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-311-5/+25
| | | | | | | | | These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. llvm-svn: 183011
* Add LLVM support for Swift.Bob Wilson2012-09-291-0/+21
| | | | llvm-svn: 164899
* Added the missing bit definition for the 4th bit of the STR (post reg) ↵Silviu Baranga2012-05-111-0/+2
| | | | | | instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. llvm-svn: 156609
* ARM: Update NEON assembly two-operand aliases.Jim Grosbach2012-04-201-1/+0
| | | | | | | | Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases for NEON instructions. There's still more to go, but this is a good chunk of them. llvm-svn: 155210
* Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga2012-04-181-0/+1
| | | | llvm-svn: 155004
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Teach the MC and disassembler about SoftFail, and hook it up to ↵James Molloy2012-02-091-0/+8
| | | | | | UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. llvm-svn: 150169
* NEON add correct predicates for some asm aliases.Jim Grosbach2012-01-241-0/+9
| | | | llvm-svn: 148815
* Simplify some NEON assembly pseudo definitions.Jim Grosbach2012-01-231-69/+0
| | | | | | | Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. llvm-svn: 148718
* ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.Jim Grosbach2011-12-221-0/+3
| | | | | | | | | | The value from the operands isn't right yet, but we weren't encoding it at all previously. The parser needs to twiddle the values when building the instruction. Partial for: rdar://10558523 llvm-svn: 147170
* ARM add more 'gas' compatibility aliases for NEON instructions.Jim Grosbach2011-12-131-0/+6
| | | | llvm-svn: 146507
* ARM VSHR implied destination operand form aliases.Jim Grosbach2011-12-081-0/+8
| | | | llvm-svn: 146192
* ARM tidy up and remove no longer needed InstAlias definitions.Jim Grosbach2011-12-071-67/+8
| | | | | | The TokenAlias handling of data type suffices renders these unnecessary. llvm-svn: 146010
* ARM Implement ARM ARM Table A7-3 via TokenAlias.Jim Grosbach2011-12-071-0/+20
| | | | | | | | | Data type suffix aliasing. Previously handled via lots of instruction aliases. Cleanup of those forthcoming. rdar://10435076 llvm-svn: 146007
* ARM assembly parsing for the rest of the VMUL data type aliases.Jim Grosbach2011-12-051-1/+1
| | | | | | Finish up rdar://10522016. llvm-svn: 145846
* ARM assmebler parsing for two-operand VMUL instructions.Jim Grosbach2011-12-051-0/+2
| | | | | | | | | Combined destination and first source operand for f32 variant of the VMUL (by scalar) instruction. rdar://10522016 llvm-svn: 145842
* ARM VLD1 single lane assembly parsing.Jim Grosbach2011-12-021-2/+2
| | | | llvm-svn: 145712
* Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.Jim Grosbach2011-12-021-15/+92
| | | | | | Add the 16-bit lane variants while I'm at it. llvm-svn: 145693
* ARM assembly parsing for data type suffices on NEON VMOV aliases.Jim Grosbach2011-11-151-0/+17
| | | | llvm-svn: 144722
* Split out the plain '.{8|16|32|64}' suffix handling.Jim Grosbach2011-11-141-8/+24
| | | | | | | Make it easier to deal with aliases for instructions that do require a suffix but accept more specific variants of the same size. llvm-svn: 144588
* ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.Jim Grosbach2011-11-141-1/+20
| | | | | | rdar://10435076 llvm-svn: 144587
* ARM VLDR/VSTR instructions don't need a size suffix.Jim Grosbach2011-11-141-0/+2
| | | | | | | Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. llvm-svn: 144583
* ARM assembly parsing type suffix options for VLDR/VSTR.Jim Grosbach2011-11-141-0/+19
| | | | | | rdar://10435076 llvm-svn: 144575
* ARM refactor simple immediate asm operand render methods.Jim Grosbach2011-11-121-2/+2
| | | | | | | These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. llvm-svn: 144439
* ARM assembly parsing for ASR(immediate).Jim Grosbach2011-11-101-7/+13
| | | | | | Start of rdar://9704684 llvm-svn: 144293
* ARM VLD/VST assembly parsing for symbolic address operands.Jim Grosbach2011-11-011-0/+20
| | | | llvm-svn: 143413
* Reapply r143202, with a manual decoding hook for SWP. This change ↵Owen Anderson2011-10-281-0/+2
| | | | | | inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. llvm-svn: 143208
* ARM NEON assembly parsing and encoding for VDUP(scalar).Jim Grosbach2011-10-071-1/+0
| | | | llvm-svn: 141446
* ARM assembly parsing and encoding for VMRS/FMSTAT.Jim Grosbach2011-10-031-0/+4
| | | | llvm-svn: 141025
* Port more encoding tests to decoding tests, and correct an improper Thumb2 ↵Owen Anderson2011-09-121-0/+4
| | | | | | pre-indexed load decoding this uncovered. llvm-svn: 139522
* Thumb2 assembly parsing and encoding for LDRD(immediate).Jim Grosbach2011-09-081-9/+8
| | | | | | Refactor operand handling for STRD as well. Tests for that forthcoming. llvm-svn: 139322
* Thumb2 assembly parsing and encoding for LDR post-indexed.Jim Grosbach2011-09-081-3/+3
| | | | | | | More cleanup of the general indexed addressing T2 instructions. Still more to do, especially for stores. llvm-svn: 139272
* Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.Jim Grosbach2011-09-081-6/+36
| | | | | | | Adjust encoding of writeback load/store instructions to better reflect the way the operand types are represented. llvm-svn: 139270
* Fix Thumb2 decoding of CPS instructions to mirror ARM decoding of the same ↵Owen Anderson2011-08-231-1/+0
| | | | | | instructions. llvm-svn: 138339
* Reject invalid imod values in t2CPS instructions.Owen Anderson2011-08-221-0/+1
| | | | llvm-svn: 138306
* Clean up predicates on ARM target instruction aliases.Jim Grosbach2011-08-221-0/+11
| | | | llvm-svn: 138249
* Thumb assembly parsing and encoding for MOV.Jim Grosbach2011-08-191-1/+1
| | | | llvm-svn: 138076
* Tidy up. Tab character.Jim Grosbach2011-08-191-1/+1
| | | | llvm-svn: 138072
* Tab characters.Jim Grosbach2011-08-191-2/+2
| | | | llvm-svn: 138066
* Separate out Thumb1 instructions that need an S bit operand from those that ↵Owen Anderson2011-08-161-0/+1
| | | | | | do not, for the purposes of decoding them. llvm-svn: 137787
* ARM thumb assembly parsing for arithmetic flag setting instructions.Jim Grosbach2011-08-161-0/+6
| | | | | | | | | Thumb one requires that many arithmetic instruction forms have an 'S' suffix. For Thumb2, the whether the suffix is required or precluded depends on whether the instruction is in an IT block. Use target parser predicates to check for these sorts of context-sensitive constraints. llvm-svn: 137746
* Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the ↵Owen Anderson2011-08-151-2/+4
| | | | | | Thumb2 NEON decoding hooks to bring us closer to correctness. llvm-svn: 137686
* Remove dead classes.Owen Anderson2011-08-151-33/+0
| | | | llvm-svn: 137643
* Update comment to reflect MC target machine refactor.Jim Grosbach2011-08-151-1/+1
| | | | llvm-svn: 137615
* Fix decoding of ARM-mode STRH.Owen Anderson2011-08-121-0/+1
| | | | llvm-svn: 137499
* Tidy up. Remove unused template parameter.Jim Grosbach2011-08-111-1/+1
| | | | llvm-svn: 137345
* ARM STRD assembly parsing and encoding.Jim Grosbach2011-08-111-29/+0
| | | | llvm-svn: 137342
* Continue to tighten decoding by performing more operand validation.Owen Anderson2011-08-111-0/+1
| | | | llvm-svn: 137340
* Add initial support for decoding NEON instructions in Thumb2 mode.Owen Anderson2011-08-101-2/+4
| | | | llvm-svn: 137236
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