| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Enhance the FixedLengthDecoder to be able to generate plausible-looking decod... | Owen Anderson | 2011-07-19 | 1 | -2/+11 |
| * | Add a target-indepedent entry to MCInstrDesc to describe the encoded size of ... | Owen Anderson | 2011-07-13 | 1 | -110/+99 |
| * | Parameterize away the ARM T1Cop class. | Jim Grosbach | 2011-07-13 | 1 | -7/+2 |
| * | Fix predicates for Thumb co-processor instructions. | Jim Grosbach | 2011-07-13 | 1 | -8/+6 |
| * | Use TableGen'erated pseudo lowering for ARM. | Jim Grosbach | 2011-07-08 | 1 | -0/+19 |
| * | Mark ARM pseudo-instructions as isPseudo. | Jim Grosbach | 2011-07-06 | 1 | -5/+3 |
| * | Make the branch encoding for tBcc more obvious that it's a 4-byte opcode | Eric Christopher | 2011-05-27 | 1 | -0/+4 |
| * | 80 columns. | Jim Grosbach | 2011-05-19 | 1 | -9/+12 |
| * | Add a few ARM coprocessor intrinsics. Testcases included | Bruno Cardoso Lopes | 2011-05-03 | 1 | -0/+8 |
| * | Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong. | Johnny Chen | 2011-04-06 | 1 | -0/+2 |
| * | - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT | Bruno Cardoso Lopes | 2011-04-04 | 1 | -0/+41 |
| * | Apply again changes to support ARM memory asm parsing. I removed | Bruno Cardoso Lopes | 2011-03-31 | 1 | -0/+18 |
| * | Revert r128632 again, until I figure out what break the tests | Bruno Cardoso Lopes | 2011-03-31 | 1 | -6/+6 |
| * | Reapply r128585 without generating a lib depedency cycle. An updated log: | Bruno Cardoso Lopes | 2011-03-31 | 1 | -6/+6 |
| * | Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and" | Matt Beaumont-Gay | 2011-03-31 | 1 | -6/+6 |
| * | Somehow we managed to forget to encode the lane index for a large swathe of N... | Owen Anderson | 2011-03-30 | 1 | -1/+50 |
| * | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and | Bruno Cardoso Lopes | 2011-03-30 | 1 | -6/+6 |
| * | Add asm parsing support w/ testcases for strex/ldrex family of instructions | Bruno Cardoso Lopes | 2011-03-24 | 1 | -2/+2 |
| * | Remove some dead patterns. | Jim Grosbach | 2011-03-14 | 1 | -10/+0 |
| * | Pseudo-instructions are codegenonly by definition. | Jim Grosbach | 2011-03-10 | 1 | -0/+1 |
| * | Rename the narrow shift right immediate operands to "shr_imm*" operands. Also | Bill Wendling | 2011-03-07 | 1 | -13/+18 |
| * | Narrow right shifts need to encode their immediates differently from a normal | Bill Wendling | 2011-03-01 | 1 | -0/+16 |
| * | Change VFPNeonA8 definition to make the code easier to read. | Evan Cheng | 2011-02-23 | 1 | -1/+1 |
| * | VFP single precision arith instructions can go down to NEON pipeline, but on ... | Evan Cheng | 2011-02-22 | 1 | -3/+4 |
| * | Add assembly parsing support for "msr" and also fix its encoding. Also add | Bruno Cardoso Lopes | 2011-02-18 | 1 | -0/+7 |
| * | Some single precision VFP instructions may be executed on NEON pipeline, but ... | Evan Cheng | 2011-02-16 | 1 | -4/+4 |
| * | Fix encoding and add parsing support for the arm/thumb CPS instruction: | Bruno Cardoso Lopes | 2011-02-14 | 1 | -0/+16 |
| * | AsmMatcher custom operand parser failure enhancements. | Jim Grosbach | 2011-02-12 | 1 | -1/+1 |
| * | Add support for parsing dmb/dsb instructions | Bruno Cardoso Lopes | 2011-02-07 | 1 | -0/+6 |
| * | Add mcr*2 and mr*c2 support to thumb2 targets | Bruno Cardoso Lopes | 2011-01-20 | 1 | -0/+6 |
| * | Add mcr* and mr*c support to thumb targets | Bruno Cardoso Lopes | 2011-01-20 | 1 | -0/+7 |
| * | Add a FIXME. | Jim Grosbach | 2011-01-18 | 1 | -0/+1 |
| * | The new t2LEApcrel* pseudo instructions need the size specified. | Jim Grosbach | 2010-12-15 | 1 | -0/+7 |
| * | Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and frie... | Owen Anderson | 2010-12-10 | 1 | -0/+1 |
| * | Tidy up. | Jim Grosbach | 2010-12-10 | 1 | -11/+8 |
| * | Trailing whitespace. | Jim Grosbach | 2010-12-10 | 1 | -5/+5 |
| * | Fix Thumb2 encoding of the S bit. | Owen Anderson | 2010-12-07 | 1 | -0/+3 |
| * | The ARM AsmMatcher needs to know that the CCOut operand is a register value, | Jim Grosbach | 2010-12-06 | 1 | -0/+7 |
| * | Add a post encoder method to the VFP instructions to convert them to the Thumb2 | Bill Wendling | 2010-12-01 | 1 | -1/+5 |
| * | Add correct encodings for STRD and LDRD, including fixup support. Additional... | Owen Anderson | 2010-12-01 | 1 | -0/+9 |
| * | General cleanups of comments. | Bill Wendling | 2010-12-01 | 1 | -11/+7 |
| * | s/T1pIEncode/T1pILdStEncode/g | Bill Wendling | 2010-12-01 | 1 | -6/+6 |
| * | Renaming variables to coincide with documentation. No functionality change. | Bill Wendling | 2010-12-01 | 1 | -1/+1 |
| * | Rename operands to match ARM documentation. No functionality change. | Bill Wendling | 2010-11-30 | 1 | -2/+2 |
| * | Inline classes that were used in only one place. | Bill Wendling | 2010-11-30 | 1 | -5/+2 |
| * | * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as | Bill Wendling | 2010-11-30 | 1 | -12/+31 |
| * | Pseudo-ize BX_CALL and friends. Remove dead instruction format classes. | Jim Grosbach | 2010-11-30 | 1 | -13/+0 |
| * | Correct Thumb2 encodings for a much wider range of loads and stores. | Owen Anderson | 2010-11-30 | 1 | -0/+9 |
| * | Parameterize ARMPseudoInst size property. | Jim Grosbach | 2010-11-29 | 1 | -4/+2 |
| * | ARM Pseudo-ize tBR_JTr. | Jim Grosbach | 2010-11-29 | 1 | -3/+7 |
