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path: root/llvm/lib/Target/ARM/ARMInstrFormats.td
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* Update ARM Insn encoding to get endian-ness to match the documentation (31-0 ...Jim Grosbach2008-10-141-23/+19
* Fix addrmode1 instruction encodings; fix bx_ret encoding.Evan Cheng2008-09-171-7/+0
* Specify instruction encoding using range list to avoid endianess issues.Evan Cheng2008-09-171-25/+26
* Revert 56176. All those instruction formats are still needed.Evan Cheng2008-09-131-9/+20
* Eliminate unnecessary instruction formats.Evan Cheng2008-09-121-20/+9
* Addrmode 1 S bit can be dynamically set. Look for CPSR def.Evan Cheng2008-09-121-2/+0
* Control flow instruction encodings.Evan Cheng2008-09-011-12/+66
* ldm / stm instruction encodings.Evan Cheng2008-09-011-3/+25
* AXI2 and AXI3 instruction encodings.Evan Cheng2008-09-011-0/+84
* Reorganize instruction formats again; AXI1 encoding.Evan Cheng2008-09-011-34/+35
* addrmode3 instruction encodings.Evan Cheng2008-09-011-28/+194
* Reorganize some instruction format definitions. No functionality change.Evan Cheng2008-09-011-18/+29
* Rest of addrmode2 instruction encodings.Evan Cheng2008-09-011-4/+96
* Addr2 word / byte load encodings.Evan Cheng2008-08-311-1/+21
* Addr1 instructions opcodes are encoded in bits 21-24; encode S bit.Evan Cheng2008-08-311-4/+5
* addrmode1 (data processing) instruction encoding: bits 5-6 are 0, bits 7-10 e...Evan Cheng2008-08-291-3/+10
* More refactoring.Evan Cheng2008-08-291-0/+55
* Refactor ARM instruction format definitions into a separate file. No function...Evan Cheng2008-08-281-0/+228
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