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path: root/llvm/lib/Target/ARM/ARMISelLowering.h
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* Framework for atomic binary operations. The emitter for the pseudo instructionsJim Grosbach2009-12-121-2/+7
| | | | | | | just issues an error for the moment. The front end won't yet generate these intrinsics for ARM, so this is behind the scenes until complete. llvm-svn: 91200
* Rough first pass at compare_and_swap atomic builtins for ARM mode. Work in ↵Jim Grosbach2009-12-111-0/+4
| | | | | | progress. llvm-svn: 91090
* Add memory barrier intrinsic support for ARM. Moving towards adding the ↵Jim Grosbach2009-12-101-0/+3
| | | | | | atomic operations intrinsics. llvm-svn: 91003
* isLegalICmpImmediate should take a signed integer; code clean up.Evan Cheng2009-11-121-1/+8
| | | | llvm-svn: 86964
* Add TargetLowering::isLegalICmpImmediate. It tells LSR what immediate can be ↵Evan Cheng2009-11-111-0/+6
| | | | | | folded into target icmp instructions. llvm-svn: 86858
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-2/+2
| | | | llvm-svn: 86494
* Add ARM codegen for indirect branches.Bob Wilson2009-10-301-0/+1
| | | | | | clang/test/CodeGen/indirect-goto.c runs! (unoptimized) llvm-svn: 85577
* Use fconsts and fconstd to materialize small fp constants.Evan Cheng2009-10-281-0/+13
| | | | llvm-svn: 85362
* ARM does not support offset folding (yet). Disable it for now.Anton Korobeynikov2009-09-231-0/+1
| | | | | | This fixes PR5031. Unfortunately, there is no small testcase :( llvm-svn: 82643
* Enhance EmitInstrWithCustomInserter() so target can specify CFG changes that ↵Evan Cheng2009-09-181-1/+2
| | | | | | | | sdisel will use to properly complete phi nodes. Not functionality change yet. llvm-svn: 82273
* Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson.Sandeep Patel2009-09-021-5/+5
| | | | llvm-svn: 80773
* Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations.Bob Wilson2009-08-261-8/+0
| | | | | | | | The instructions can be selected directly from the intrinsics. We will need to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but those are not yet implemented. llvm-svn: 80117
* Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,Bob Wilson2009-08-211-3/+2
| | | | | | now using shuffles instead of intrinsics. llvm-svn: 79673
* Fix some typos and use type-based isel for VZIP/VUZP/VTRNAnton Korobeynikov2009-08-211-9/+3
| | | | llvm-svn: 79625
* Add lowering of ARM 4-element shuffles to multiple instructios via ↵Anton Korobeynikov2009-08-211-1/+11
| | | | | | perfectshuffle-generated table. llvm-svn: 79624
* Use masks not nodes for vector shuffle predicates. Provide set of 'legal' ↵Anton Korobeynikov2009-08-211-0/+1
| | | | | | masks, so legalizer won't infinite cycle llvm-svn: 79619
* Add support for Neon VEXT (vector extract) shuffles.Bob Wilson2009-08-191-0/+1
| | | | | | | | This is derived from a patch by Anton Korzh. I modified it to recognize the VEXT shuffles during legalization and lower them to a target-specific DAG node. llvm-svn: 79428
* Reapply r79127. It was fixed by d0k.Bill Wendling2009-08-151-0/+7
| | | | llvm-svn: 79136
* Revert r79127. It was causing compilation errors.Bill Wendling2009-08-151-7/+0
| | | | llvm-svn: 79135
* Change allowsUnalignedMemoryAccesses to take type argument since some targetsEvan Cheng2009-08-151-0/+7
| | | | | | | | | | support unaligned mem access only for certain types. (Should it be size instead?) ARM v7 supports unaligned access for i16 and i32, some v6 variants support it as well. llvm-svn: 79127
* Add Thumb2 lsr hooks.Evan Cheng2009-08-141-0/+1
| | | | llvm-svn: 79032
* Create a new ARM-specific DAG node, VDUP, to represent a splat from aBob Wilson2009-08-141-1/+2
| | | | | | | scalar_to_vector. Generate these VDUP nodes during legalization instead of trying to recognize the pattern during selection. llvm-svn: 78994
* During legalization, change Neon vdup_lane operations from shuffles toBob Wilson2009-08-141-2/+2
| | | | | | | | target-specific VDUPLANE nodes. This allows the subreg handling for the quad-register version to be done easily with Pats in the .td file, instead of with custom code in ARMISelDAGToDAG.cpp. llvm-svn: 78993
* Revert r78852 for now. I want to do this differently, but I don't have timeBob Wilson2009-08-131-2/+1
| | | | | | to fix it tonight. llvm-svn: 78896
* Recognize Neon VDUP shuffles during legalization instead of selection.Bob Wilson2009-08-121-1/+2
| | | | llvm-svn: 78852
* Recognize Neon VREV shuffles during legalization instead of selection.Bob Wilson2009-08-121-6/+6
| | | | llvm-svn: 78850
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-5/+5
| | | | | | own struct type. llvm-svn: 78610
* It turns out most of the thumb2 instructions are not allowed to touch SP. ↵Evan Cheng2009-08-071-2/+5
| | | | | | | | | | The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing. This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time. This fixes PR4659 and PR4682. llvm-svn: 78361
* Implement Neon VST[234] operations.Bob Wilson2009-08-061-1/+4
| | | | llvm-svn: 78330
* Missed pieces for ARM HardFP ABI.Anton Korobeynikov2009-08-051-1/+1
| | | | | | Patch by Sandeep Patel! llvm-svn: 78225
* Major calling convention code refactoring.Dan Gohman2009-08-051-9/+32
| | | | | | | | | | | | | | | | | | | Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. llvm-svn: 78142
* Lower Neon VLD* intrinsics to custom DAG nodes, and manually allocate theBob Wilson2009-08-041-1/+7
| | | | | | results to fixed registers. llvm-svn: 78025
* Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte ↵Evan Cheng2009-07-291-0/+1
| | | | | | / halfword. llvm-svn: 77422
* In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is ↵Evan Cheng2009-07-281-1/+0
| | | | | | until more optimization goes in). llvm-svn: 77364
* Add support for ARM Neon VREV instructions.Bob Wilson2009-07-261-0/+5
| | | | | | Patch by Anton Korzh, with some modifications from me. llvm-svn: 77101
* Change Thumb2 jumptable codegen to one that uses two level jumps:Evan Cheng2009-07-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before: adr r12, #LJTI3_0_0 ldr pc, [r12, +r0, lsl #2] LJTI3_0_0: .long LBB3_24 .long LBB3_30 .long LBB3_31 .long LBB3_32 After: adr r12, #LJTI3_0_0 add pc, r12, +r0, lsl #2 LJTI3_0_0: b.w LBB3_24 b.w LBB3_30 b.w LBB3_31 b.w LBB3_32 This has several advantages. 1. This will make it easier to optimize this to a TBB / TBH instruction + (smaller) table. 2. This eliminate the need for ugly asm printer hack to force the address into thumb addresses (bit 0 is one). 3. Same codegen for pic and non-pic. 4. This eliminate the need to align the table so constantpool island pass won't have to over-estimate the size. Based on my calculation, the later is probably slightly faster as well since ldr pc with shifter address is very slow. That is, it should be a win as long as the HW implementation can do a reasonable job of branch predict the second branch. llvm-svn: 77024
* Fix comment typos.Bob Wilson2009-07-131-1/+1
| | | | llvm-svn: 75479
* Update comments to make it clear that the function alignment is the Log2 of theBill Wendling2009-07-011-1/+1
| | | | | | bytes and not bytes. llvm-svn: 74624
* Add an "alignment" field to the MachineFunction object. It makes more sense toBill Wendling2009-06-301-0/+3
| | | | | | | | | | have the alignment be calculated up front, and have the back-ends obey whatever alignment is decided upon. This allows for future work that would allow for precise no-op placement and the like. llvm-svn: 74564
* Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only ↵David Goodwin2009-06-291-1/+1
| | | | | | the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. llvm-svn: 74423
* Add support for ARM's Advanced SIMD (NEON) instruction set.Bob Wilson2009-06-221-1/+71
| | | | | | | This is still a work in progress but most of the NEON instruction set is supported. llvm-svn: 73919
* Address review comments: add 3 ARM calling conventions.Anton Korobeynikov2009-06-161-0/+1
| | | | | | | Dispatch C calling conv. to one of these conventions based on target triple and subtarget features. llvm-svn: 73530
* Minor formatting fixes.Bob Wilson2009-05-201-2/+2
| | | | llvm-svn: 72172
* Update the names of the exception handling sjlj instrinsics toJim Grosbach2009-05-141-2/+2
| | | | | | | | | llvm.eh.sjlj.* for better clarity as to their purpose and scope. Add a description of llvm.eh.sjlj.setjmp to ExceptionHandling.html. (llvm.eh.sjlj.longjmp documentation coming when that implementation is added). llvm-svn: 71758
* Spelling correction s/builting/builtin/ and remove trailing whitespace in a ↵Jim Grosbach2009-05-131-10/+10
| | | | | | few places llvm-svn: 71735
* Add support for GCC compatible builtin setjmp and longjmp intrinsics. This isJim Grosbach2009-05-121-0/+5
| | | | | | | a supporting preliminary patch for GCC-compatible SjLJ exception handling. Note that these intrinsics are not designed to be invoked directly by the user, but rather used by the front-end as target hooks for exception handling. llvm-svn: 71610
* Clean up formatting, remove trailing whitespace, fix comment typos andBob Wilson2009-04-171-3/+2
| | | | | | punctuation. No functional changes. llvm-svn: 69378
* Use CallConvLower.h and TableGen descriptions of the calling conventionsBob Wilson2009-04-171-0/+8
| | | | | | for ARM. Patch by Sandeep Patel. llvm-svn: 69371
* Fix PR3862: Recognize some ARM-specific constraints for immediates in inlineBob Wilson2009-04-011-0/+10
| | | | | | assembly. llvm-svn: 68218
* Constify TargetInstrInfo::EmitInstrWithCustomInserter, allowingDan Gohman2009-02-071-1/+1
| | | | | | ScheduleDAG's TLI member to use const. llvm-svn: 64018
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