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* Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-111-0/+22
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Third attempt: simplified checks in test for armv7-apple-darwin11. llvm-svn: 146341
* Revert r146322 to appease buildbots. Original commit message:Chad Rosier2011-12-101-22/+0
| | | | | | | | Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. llvm-svn: 146328
* Fixed bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-101-0/+22
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). Second attempt. llvm-svn: 146322
* Splats can contain undef's; make sure to handle them correctly. PR11526.Eli Friedman2011-12-091-2/+1
| | | | llvm-svn: 146299
* Revert r146143, "Fix bug 9905: Failure in code selection for llvm intrinsicsDaniel Dunbar2011-12-081-22/+0
| | | | | | | sqrt/exp (fix for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2).", it is failing tests. llvm-svn: 146157
* Fix bug 9905: Failure in code selection for llvm intrinsics sqrt/exp (fix ↵Stepan Dyatkovskiy2011-12-081-0/+22
| | | | | | for FSQRT, FSIN, FCOS, FPOWI, FPOW, FLOG, FLOG2, FLOG10, FEXP, FEXP2). llvm-svn: 146143
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-4/+4
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-9/+14
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Move code into anonymous namespaces.Benjamin Kramer2011-11-261-1/+1
| | | | llvm-svn: 145154
* Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>Bob Wilson2011-11-161-59/+2
| | | | | | | | | | | | | | | | | The EmitBasePointerRecalculation function has 2 problems, one minor and one fatal. The minor problem is that it inserts the code at the setjmp instead of in the dispatch block. The fatal problem is that at the point where this code runs, we don't know whether there will be a base pointer, so the entire function is a no-op. The base pointer recalculation needs to be handled as it was before, by inserting a pseudo instruction that gets expanded late. Most of the support for the old approach is still here, but it no longer has any connection to the eh_sjlj_dispatchsetup intrinsic. Clean up the parts related to the intrinsic and just generate the pseudo instruction directly. llvm-svn: 144781
* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-151-1/+0
| | | | llvm-svn: 144631
* Add vmov.f32 to materialize f32 immediate splats which cannot be handled byEvan Cheng2011-11-151-0/+11
| | | | | | integer variants. rdar://10437054 llvm-svn: 144608
* Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.Eli Friedman2011-11-111-0/+1
| | | | llvm-svn: 144361
* Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.Eli Friedman2011-11-091-1/+25
| | | | llvm-svn: 144241
* Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.Lang Hames2011-11-081-0/+7
| | | | | | | | Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. llvm-svn: 144102
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-081-31/+36
| | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
* Make sure to mark vector extload's as expand on ARM. Fixes PR11319.Eli Friedman2011-11-081-9/+11
| | | | llvm-svn: 144057
* Reapply r143206, with fixes. Disallow physical register lifetimesDan Gohman2011-11-031-3/+16
| | | | | | | across calls, and only check for nested dependences on the special call-sequence-resource register. llvm-svn: 143660
* Fixed parameter name.Lang Hames2011-11-021-2/+2
| | | | llvm-svn: 143594
* Try to lower memset/memcpy/memmove to vector instructions on ARM where the ↵Lang Hames2011-11-021-0/+28
| | | | | | alignment permits. llvm-svn: 143582
* Revert r143206, as there are still some failing tests.Dan Gohman2011-10-291-16/+3
| | | | llvm-svn: 143262
* Reapply r143177 and r143179 (reverting r143188), with schedulerDan Gohman2011-10-281-3/+16
| | | | | | | | | fixes: Use a separate register, instead of SP, as the calling-convention resource, to avoid spurious conflicts with actual uses of SP. Also, fix unscheduling of calling sequences, which can be triggered by pseudo-two-address dependencies. llvm-svn: 143206
* Speculatively disable Dan's commits 143177 and 143179 to see ifDuncan Sands2011-10-281-16/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | it fixes the dragonegg self-host (it looks like gcc is miscompiled). Original commit messages: Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. Delete #if 0 code accidentally left in. llvm-svn: 143188
* Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman2011-10-281-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. llvm-svn: 143177
* Make sure short memsets on ARM lower to stores, even when optimizing for size.Lang Hames2011-10-261-0/+2
| | | | llvm-svn: 143055
* Revert r142530 at least temporarily while a discussion is had on ↵James Molloy2011-10-261-5/+2
| | | | | | llvm-commits regarding exactly how much optsize should optimize for size over performance. llvm-svn: 143023
* Use a worklist to prevent the iterator from becoming invalidated because of ↵Bill Wendling2011-10-261-3/+4
| | | | | | the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot. llvm-svn: 143018
* Revert part of r142530. The patch potentially hurts performance especiallyEvan Cheng2011-10-261-3/+3
| | | | | | | on Darwin platforms where -Os means optimize for size without hurting performance. llvm-svn: 143002
* Don't crash on variable insertelement on ARM. PR10258.Eli Friedman2011-10-241-0/+11
| | | | llvm-svn: 142871
* Change this overloaded use of Sched::Latency to be an overloadedDan Gohman2011-10-241-2/+2
| | | | | | use of Sched::ILP instead, as Sched::Latency is going away. llvm-svn: 142813
* The different flavors of ARM have different valid subsets of registers. CheckBill Wendling2011-10-221-3/+13
| | | | | | | that the set of callee-saved registers is correct for the specific platform. <rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2 llvm-svn: 142706
* Add missing operand. <rdar://problem/10313323>Bill Wendling2011-10-201-1/+2
| | | | llvm-svn: 142615
* Use literal pool loads instead of MOVW/MOVT for materializing global ↵James Molloy2011-10-191-3/+6
| | | | | | | | | | | | | | addresses when optimizing for size. On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is codesize including literal pools. The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries. Fixes PR11087. llvm-svn: 142530
* Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, ↵Bill Wendling2011-10-191-5/+27
| | | | | | use a constant pool. llvm-svn: 142485
* Remove some dead code.Bill Wendling2011-10-191-6/+0
| | | | llvm-svn: 142484
* Emit the MOVT instruction only if the # LPads is > 64K.Bill Wendling2011-10-181-10/+20
| | | | llvm-svn: 142460
* For Thumb mode, we need to use a constant pool if the value is too large to beBill Wendling2011-10-181-3/+20
| | | | | | used with the CMP instruction. llvm-svn: 142458
* Use the integer compare when the value is small enough. Use the "move into aBill Wendling2011-10-181-2/+17
| | | | | | | register and then compare against that" method when it's too large. We have to move the value into the register in the "movw, movt" pair of instructions. llvm-svn: 142440
* Use the integer compare when the value is small enough. Use the "move into aBill Wendling2011-10-181-6/+19
| | | | | | | register and then compare against that" method when it's too large. We have to move the value into the register in the "movw, movt" pair of instructions. llvm-svn: 142437
* The value we're comparing against may be too large for the ARM CMPBill Wendling2011-10-181-12/+16
| | | | | | | instruction. Move the value into a register and then use that for the CMP. <rdar://problem/10305266> llvm-svn: 142431
* The immediate may be too large for the CMP instruction. Move it into a registerBill Wendling2011-10-181-8/+13
| | | | | | | and use that in the CMP. <rdar://problem/10305266> llvm-svn: 142429
* Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.Andrew Trick2011-10-181-7/+15
| | | | | | | | Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
* Use isIntN and isUIntN to check for valid signed/unsigned numbers.Bob Wilson2011-10-181-3/+2
| | | | llvm-svn: 142395
* whitespaceAndrew Trick2011-10-181-6/+6
| | | | llvm-svn: 142394
* A landing pad could have more than one predecessor. In that case, we want thatBill Wendling2011-10-181-1/+8
| | | | | | | | | | predecessor to remove the jump to it as well. Delay clearing the 'landing pad' flag until after the jumps have been removed. (There is an implicit assumption in several modules that an MBB which jumps to a landing pad has only two successors.) <rdar://problem/10304224> llvm-svn: 142390
* Fix incorrect check for sign-extended constant BUILD_VECTOR.Bob Wilson2011-10-181-1/+1
| | | | | | <rdar://problem/10298332> llvm-svn: 142371
* Fix a bunch of unused variable warnings when doing a releaseDuncan Sands2011-10-181-2/+2
| | | | | | build with gcc-4.6. llvm-svn: 142350
* Don't renumber the blocks here. This could cause problems later on if anotherBill Wendling2011-10-171-3/+1
| | | | | | pass renumbers the blocks again. llvm-svn: 142258
* Add a call to EmitSjLjDispatchBlock.Bill Wendling2011-10-171-0/+8
| | | | | | | Once the intrinsics are marked as having a custom inserter, it will call this method to emit the dispatch table into the machine function. llvm-svn: 142245
* Add comment explaining that the order of processing doesn't matter here.Bill Wendling2011-10-171-0/+1
| | | | llvm-svn: 142176
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