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path: root/llvm/lib/Target/ARM/ARMISelLowering.cpp
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* Set operation action for FFLOOR to Expand for all vector types for X86. Set ↵Craig Topper2012-09-081-0/+1
| | | | | | FFLOOR of v4f32 to Expand for ARM. v2f64 was already correct. llvm-svn: 163458
* Custom DAGCombine for and/or/xor are for all ARMs.Jakob Stoklund Olesen2012-09-071-6/+3
| | | | | | | The 'select' transformations apply to all ARM architectures and don't require hasV6T2Ops. llvm-svn: 163396
* Fix self-host; ensure signedness is consistent.James Molloy2012-09-061-2/+2
| | | | llvm-svn: 163306
* Improve codegen for BUILD_VECTORs on ARM.James Molloy2012-09-061-10/+56
| | | | | | If we have a BUILD_VECTOR that is mostly a constant splat, it is often better to splat that constant then insertelement the non-constant lanes instead of insertelementing every lane from an undef base. llvm-svn: 163304
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-09-041-0/+156
| | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 163136
* Fix a couple of typos in EmitAtomic.Jakob Stoklund Olesen2012-08-311-2/+2
| | | | | | | | | Thumb2 instructions are mostly constrained to rGPR, not tGPR which is for Thumb1. rdar://problem/12203728 llvm-svn: 162968
* Use a SmallPtrSet to dedup successors in EmitSjLjDispatchBlock.Jakob Stoklund Olesen2012-08-201-3/+2
| | | | | | | The test case ARM/2011-05-04-MultipleLandingPadSuccs.ll was creating duplicate successor list entries. llvm-svn: 162222
* Remove the CAND/COR/CXOR custom ISD nodes and their select code.Jakob Stoklund Olesen2012-08-181-51/+0
| | | | | | | These nodes are no longer needed because the peephole pass can fold CMOV+AND into ANDCC etc. llvm-svn: 162179
* Also combine zext/sext into selects for ARM.Jakob Stoklund Olesen2012-08-181-47/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This turns common i1 patterns into predicated instructions: (add (zext cc), x) -> (select cc (add x, 1), x) (add (sext cc), x) -> (select cc (add x, -1), x) For a function like: unsigned f(unsigned s, int x) { return s + (x>0); } We now produce: cmp r1, #0 it gt addgt.w r0, r0, #1 Instead of: movs r2, #0 cmp r1, #0 it gt movgt r2, #1 add r0, r2 llvm-svn: 162177
* Also pass logical ops to combineSelectAndUse.Jakob Stoklund Olesen2012-08-181-9/+42
| | | | | | | | | | | | | | | | Add these transformations to the existing add/sub ones: (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) (or (select cc, 0, c), x) -> (select cc, x, (or, x, c)) (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c)) The selects can then be transformed to a single predicated instruction by peephole. This transformation will make it possible to eliminate the ISD::CAND, COR, and CXOR custom DAG nodes. llvm-svn: 162176
* Add comment, clean up code. No functional change.Jakob Stoklund Olesen2012-08-171-30/+39
| | | | llvm-svn: 162107
* Handle ARM MOVCC optimization in PeepholeOptimizer.Jakob Stoklund Olesen2012-08-161-48/+0
| | | | | | Use the target independent select analysis hooks. llvm-svn: 162060
* Fold predicable instructions into MOVCC / t2MOVCC.Jakob Stoklund Olesen2012-08-151-0/+48
| | | | | | | | | | | | | | The ARM select instructions are just predicated moves. If the select is the only use of an operand, the instruction defining the operand can be predicated instead, saving one instruction and decreasing register pressure. This implementation can turn AND/ORR/EOR instructions into their corresponding ANDCC/ORRCC/EORCC variants. Ideally, we should be able to predicate any instruction, but we don't yet support predicated instructions in SSA form. llvm-svn: 161994
* Use vld1/vst1 to load/store f64 if alignment is < 4 and the target allows ↵Evan Cheng2012-08-151-0/+2
| | | | | | unaligned access. rdar://12091029 llvm-svn: 161962
* Do not optimize (or (and X,Y), Z) into BFI and other sequences if the AND ↵Nadav Rotem2012-08-131-1/+5
| | | | | | | | ISDNode has more than one user. rdar://11876519 llvm-svn: 161775
* Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARMArnold Schwaighofer2012-08-121-156/+0
| | | | | | | | | architecture It broke MultiSource/Applications/JM/ldecod/ldecod on armv7 thumb O0 g and armv7 thumb O3. llvm-svn: 161736
* Change addTypeForNeon to use MVT instead of EVT so all the calls to ↵Craig Topper2012-08-121-48/+43
| | | | | | getSimpleVT can be removed. llvm-svn: 161735
* Patch to implement UMLAL/SMLAL instructions for the ARM architectureArnold Schwaighofer2012-08-091-0/+156
| | | | | | | | | | | This patch corrects the definition of umlal/smlal instructions and adds support for matching them to the ARM dag combiner. Bug 12213 Patch by Yin Ma! llvm-svn: 161581
* Fall back to selection DAG isel for calls to builtin functions.Bob Wilson2012-08-031-2/+3
| | | | | | | | | | Fast isel doesn't currently have support for translating builtin function calls to target instructions. For embedded environments where the library functions are not available, this is a matter of correctness and not just optimization. Most of this patch is just arranging to make the TargetLibraryInfo available in fast isel. <rdar://problem/12008746> llvm-svn: 161232
* Add support for the ARM GHC calling convention, this patch was in 3.0,Eric Christopher2012-08-031-0/+2
| | | | | | | | but somehow managed to be dropped later. Patch by Karel Gardas. llvm-svn: 161226
* ARM: Don't assume an SDNode is a constant.Jim Grosbach2012-07-251-0/+4
| | | | | | | | | Before accessing a node as a ConstandSDNode, make sure it actually is one. No testcase of non-trivial size. rdar://11948669 llvm-svn: 160735
* Fix ARMTargetLowering::isLegalAddImmediate to consider thumb encodings.Andrew Trick2012-07-181-4/+11
| | | | | | Based on Evan's suggestion without a commitable test. llvm-svn: 160441
* whitespaceAndrew Trick2012-07-181-2/+2
| | | | llvm-svn: 160440
* ARM: use NOEN loads and stores if possible when handling struct byval.Manman Ren2012-06-181-8/+42
| | | | | | | | This change is to be enabled in clang. rdar://9877866 llvm-svn: 158684
* ARM: optimization for sub+abs.Manman Ren2012-06-151-11/+6
| | | | | | | | | | | | | | This patch will optimize abs(x-y) FROM sub, movs, rsbmi TO subs, rsbmi For abs, we will use cmp instead of movs. This is necessary because we already have an existing peephole pass which optimizes away cmp following sub. rdar: 11633193 llvm-svn: 158551
* Re-enable the CMN instruction.Bill Wendling2012-06-111-0/+1
| | | | | | | | | We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
* ARM: properly handle alignment for struct byval.Manman Ren2012-06-011-246/+268
| | | | | | | | | Factor out the expansion code into a function. This change is to be enabled in clang. rdar://9877866 llvm-svn: 157830
* ARM: support struct byval in llvmManman Ren2012-06-011-15/+262
| | | | | | | | | | We handle struct byval by inserting a pseudo op, which will be expanded to a loop at ExpandISelPseudos. A separate patch for clang will be submitted to enable struct byval. rdar://9877866 llvm-svn: 157793
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-251-9/+16
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* Use the right register class for LDRrs.Jakob Stoklund Olesen2012-05-201-1/+1
| | | | llvm-svn: 157152
* Add a new target hook "predictableSelectIsExpensive".Benjamin Kramer2012-05-051-0/+3
| | | | | | | | | | | This will be used to determine whether it's profitable to turn a select into a branch when the branch is likely to be predicted. Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM. I'm not entirely happy with the name of this flag, suggestions welcome ;) llvm-svn: 156233
* Pacify GCC's -Wreturn-typeMatt Beaumont-Gay2012-05-041-0/+1
| | | | llvm-svn: 156189
* Make ARM and Mips use TargetMachine::getTLSModel()Hans Wennborg2012-05-041-8/+15
| | | | | | | | This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). llvm-svn: 156162
* Don't introduce illegal types when creating vmull operations. <rdar://11324364>Bob Wilson2012-04-301-1/+3
| | | | | | | | ARM BUILD_VECTORs created after type legalization cannot use i8 or i16 operands, since those types are not legal. Instead use i32 operands, which will be implicitly truncated by the BUILD_VECTOR to match the element type. llvm-svn: 155824
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-69/+74
| | | | | | since they are equivalent. llvm-svn: 155188
* Handle llvm.fma.* intrinsics. rdar://10914096Evan Cheng2012-04-101-2/+4
| | | | llvm-svn: 154439
* Fix a long standing tail call optimization bug. When a libcall is emittedEvan Cheng2012-04-101-33/+42
| | | | | | | | | | | | | legalizer always use the DAG entry node. This is wrong when the libcall is emitted as a tail call since it effectively folds the return node. If the return node's input chain is not the entry (i.e. call, load, or store) use that as the tail call input chain. PR12419 rdar://9770785 rdar://11195178 llvm-svn: 154370
* When performing a truncating store, it's possible to rearrange the data Chad Rosier2012-04-091-1/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in-register, such that we can use a single vector store rather then a series of scalar stores. For func_4_8 the generated code vldr d16, LCPI0_0 vmov d17, r0, r1 vadd.i16 d16, d17, d16 vmov.u16 r0, d16[3] strb r0, [r2, #3] vmov.u16 r0, d16[2] strb r0, [r2, #2] vmov.u16 r0, d16[1] strb r0, [r2, #1] vmov.u16 r0, d16[0] strb r0, [r2] bx lr becomes vldr d16, LCPI0_0 vmov d17, r0, r1 vadd.i16 d16, d17, d16 vuzp.8 d16, d17 vst1.32 {d16[0]}, [r2, :32] bx lr I'm not fond of how this combine pessimizes 2012-03-13-DAGCombineBug.ll, but I couldn't think of a way to judiciously apply this combine. This ldrh r0, [r0, #4] strh r0, [r1] becomes vldr d16, [r0] vmov.u16 r0, d16[2] vmov.32 d16[0], r0 vuzp.16 d16, d17 vst1.32 {d16[0]}, [r1, :32] PR11158 rdar://10703339 llvm-svn: 154340
* Update comments and remove unnecessary isVolatile() check.Chad Rosier2012-04-091-3/+5
| | | | llvm-svn: 154336
* Tidy up. 80 columns.Jim Grosbach2012-04-061-1/+2
| | | | llvm-svn: 154226
* There is no portable std::abs overload for int64_t, use the llvm::abs64Chandler Carruth2012-04-061-2/+2
| | | | | | which exists for this purpose. llvm-svn: 154199
* Allow negative immediates in ARM and Thumb2 compares.Jakob Stoklund Olesen2012-04-061-2/+4
| | | | | | | ARM and Thumb2 mode can use cmn instructions to compare against negative immediates. Thumb1 mode can't. llvm-svn: 154183
* Always compute all the bits in ComputeMaskedBits.Rafael Espindola2012-04-041-7/+4
| | | | | | | | This allows us to keep passing reduced masks to SimplifyDemandedBits, but know about all the bits if SimplifyDemandedBits fails. This allows instcombine to simplify cases like the one in the included testcase. llvm-svn: 154011
* ARM target should allow codegenprep to duplicate ret instructions to enable ↵Evan Cheng2012-03-301-1/+1
| | | | | | tailcall opt. rdar://11140249 llvm-svn: 153717
* Try using vmov.i32 to materialize FP32 constants that can't be materialized byLang Hames2012-03-291-23/+54
| | | | | | vmov.f32. llvm-svn: 153696
* Remove unnecessary llvm:: qualificationsCraig Topper2012-03-271-1/+1
| | | | llvm-svn: 153500
* Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper2012-03-261-1/+0
| | | | llvm-svn: 153422
* Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.Craig Topper2012-03-251-3/+2
| | | | llvm-svn: 153421
* Perform mul combine when multiplying wiht negative constants.Anton Korobeynikov2012-03-191-18/+48
| | | | | | | Patch by Weiming Zhao! This fixes PR12212 llvm-svn: 153049
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-171-2/+1
| | | | llvm-svn: 152978
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