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* Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, ↵Bill Wendling2011-10-191-5/+27
| | | | | | use a constant pool. llvm-svn: 142485
* Remove some dead code.Bill Wendling2011-10-191-6/+0
| | | | llvm-svn: 142484
* Emit the MOVT instruction only if the # LPads is > 64K.Bill Wendling2011-10-181-10/+20
| | | | llvm-svn: 142460
* For Thumb mode, we need to use a constant pool if the value is too large to beBill Wendling2011-10-181-3/+20
| | | | | | used with the CMP instruction. llvm-svn: 142458
* Use the integer compare when the value is small enough. Use the "move into aBill Wendling2011-10-181-2/+17
| | | | | | | register and then compare against that" method when it's too large. We have to move the value into the register in the "movw, movt" pair of instructions. llvm-svn: 142440
* Use the integer compare when the value is small enough. Use the "move into aBill Wendling2011-10-181-6/+19
| | | | | | | register and then compare against that" method when it's too large. We have to move the value into the register in the "movw, movt" pair of instructions. llvm-svn: 142437
* The value we're comparing against may be too large for the ARM CMPBill Wendling2011-10-181-12/+16
| | | | | | | instruction. Move the value into a register and then use that for the CMP. <rdar://problem/10305266> llvm-svn: 142431
* The immediate may be too large for the CMP instruction. Move it into a registerBill Wendling2011-10-181-8/+13
| | | | | | | and use that in the CMP. <rdar://problem/10305266> llvm-svn: 142429
* Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.Andrew Trick2011-10-181-7/+15
| | | | | | | | Clean up the patterns, fix comments, and avoid confusing both tools and coders. Note that the special adds/subs SelectionDAG nodes no longer have the dummy cc_out operand. llvm-svn: 142397
* Use isIntN and isUIntN to check for valid signed/unsigned numbers.Bob Wilson2011-10-181-3/+2
| | | | llvm-svn: 142395
* whitespaceAndrew Trick2011-10-181-6/+6
| | | | llvm-svn: 142394
* A landing pad could have more than one predecessor. In that case, we want thatBill Wendling2011-10-181-1/+8
| | | | | | | | | | predecessor to remove the jump to it as well. Delay clearing the 'landing pad' flag until after the jumps have been removed. (There is an implicit assumption in several modules that an MBB which jumps to a landing pad has only two successors.) <rdar://problem/10304224> llvm-svn: 142390
* Fix incorrect check for sign-extended constant BUILD_VECTOR.Bob Wilson2011-10-181-1/+1
| | | | | | <rdar://problem/10298332> llvm-svn: 142371
* Fix a bunch of unused variable warnings when doing a releaseDuncan Sands2011-10-181-2/+2
| | | | | | build with gcc-4.6. llvm-svn: 142350
* Don't renumber the blocks here. This could cause problems later on if anotherBill Wendling2011-10-171-3/+1
| | | | | | pass renumbers the blocks again. llvm-svn: 142258
* Add a call to EmitSjLjDispatchBlock.Bill Wendling2011-10-171-0/+8
| | | | | | | Once the intrinsics are marked as having a custom inserter, it will call this method to emit the dispatch table into the machine function. llvm-svn: 142245
* Add comment explaining that the order of processing doesn't matter here.Bill Wendling2011-10-171-0/+1
| | | | llvm-svn: 142176
* ARM cannot select a pattern for trunc-store v4i8; /ARM/vrev.ll fails when ↵Nadav Rotem2011-10-151-0/+2
| | | | | | promoting elements. llvm-svn: 142080
* Mark registers as DEAD because they're really just clobbers.Bill Wendling2011-10-151-1/+1
| | | | llvm-svn: 142027
* Add missing correctness check to ARMTargetLowering::ReconstructShuffle. ↵Eli Friedman2011-10-141-0/+8
| | | | | | Fixes PR11129. llvm-svn: 142022
* Make sure that the register is in the register class before adding it as a ↵Bill Wendling2011-10-141-1/+3
| | | | | | machine op. llvm-svn: 142021
* Mark the invoke call instruction as implicitly defining the callee-saved ↵Bill Wendling2011-10-141-2/+31
| | | | | | | | | | registers. The callee-saved registers cannot be live across an invoke call because the control flow may continue along the exceptional edge. When this happens, all of the callee-saved registers are no longer valid. llvm-svn: 142018
* Simplify and avoid undefined shift. Based on patch by Ahmed Charles.Eli Friedman2011-10-131-2/+1
| | | | llvm-svn: 141903
* Reapply r141365 now that PR11107 is fixed.Bill Wendling2011-10-101-0/+80
| | | | llvm-svn: 141591
* Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame toBill Wendling2011-10-101-80/+0
| | | | | | hang, and possibly SPEC/CINT2006/464_h264ref. llvm-svn: 141560
* Take all of the invoke basic blocks and make the dispatch basic block their newBill Wendling2011-10-071-4/+28
| | | | | | | | | | | successor. Remove the old landing pad from their successor list, because it's now the successor of the dispatch block. Now that the landing pad blocks are no longer the destination of invokes, we can mark them as normal basic blocks instead of landing pads. This more closely resembles what the CFG is actually doing. llvm-svn: 141436
* Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emitBill Wendling2011-10-071-0/+49
| | | | | | | it with the new SjLj emitter stuff. This way there's no need to emit that kind-of-hacky intrinsic. llvm-svn: 141419
* Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented toBill Wendling2011-10-071-1/+2
| | | | | | do. This will be useful later on with the new SJLJ stuff. llvm-svn: 141416
* Reenable tail calls for iOS 5.0 and later.Bob Wilson2011-10-071-2/+2
| | | | llvm-svn: 141370
* Reenable use of divmod compiler_rt functions for iOS 5.0 and later.Bob Wilson2011-10-071-0/+7
| | | | llvm-svn: 141368
* Peephole optimization for ABS on ARM.Anton Korobeynikov2011-10-071-0/+80
| | | | | | Patch by Ana Pazos! llvm-svn: 141365
* Use the correct vreg here.Bill Wendling2011-10-061-1/+1
| | | | llvm-svn: 141342
* Generate the dispatch code for a 'thumb' function. This is very similar to theBill Wendling2011-10-061-2/+53
| | | | | | | others. They take the call site value. Determine if it's a proper value. And then jumps to the correct call site via a jump table. llvm-svn: 141341
* Generate the dispatch table for ARM mode.Bill Wendling2011-10-061-29/+71
| | | | llvm-svn: 141327
* Refactor some of the code that sets up the entry block for SjLj EH. No ↵Bill Wendling2011-10-061-79/+101
| | | | | | functionality change. llvm-svn: 141323
* Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!)Bill Wendling2011-10-061-7/+12
| | | | | | Place the immediate to OR into a register so that it works. llvm-svn: 141319
* * Set the low bit of the return address when we are in thumb mode.Bill Wendling2011-10-061-73/+90
| | | | | | * Some code cleanup. llvm-svn: 141317
* Add the MBBs before inserting the instructions. Doing it afterwards could leadBill Wendling2011-10-061-28/+10
| | | | | | | | to an infinite loop because of the def-use chains. Also use a frame load instead of store for the LD instruction. llvm-svn: 141263
* Get the proper call site numbers for the landing pads. Also remove a magicBill Wendling2011-10-051-15/+27
| | | | | | number (18) for the proper addressing mode. llvm-svn: 141245
* Look at the number of entries in the jump table and jump to a 'trap' block ifBill Wendling2011-10-051-14/+50
| | | | | | the value exceeds that number. llvm-svn: 141143
* Checkpoint for SJLJ EH code.Bill Wendling2011-10-051-3/+75
| | | | | | | This is a first pass at generating the jump table for the sjlj dispatch. It currently generates something plausible, but hasn't been tested thoroughly. llvm-svn: 141140
* Use the PC label ID rather than '1'. Add support for thumb-2, because I ↵Bill Wendling2011-10-031-10/+41
| | | | | | heard that some people use it. llvm-svn: 141042
* Check-pointing the new SjLj EH lowering.Bill Wendling2011-10-031-0/+74
| | | | | | | | | | | This code will replace the version in ARMAsmPrinter.cpp. It creates a new machine basic block, which is the dispatch for the return from a longjmp call. It then shoves the address of that machine basic block into the correct place in the function context so that the EH runtime will jump to it directly instead of having to go through a compare-and-jump-to-the-dispatch bit. This should be more efficient in the common case. llvm-svn: 141031
* Use the new ARMConstantPoolSymbol class to handle external symbols.Bill Wendling2011-10-011-7/+9
| | | | llvm-svn: 140939
* Switch over to using ARMConstantPoolConstant for global variables, functions,Bill Wendling2011-10-011-18/+21
| | | | | | and block addresses. llvm-svn: 140936
* ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach2011-09-301-46/+2
| | | | | | | | | | | Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 llvm-svn: 140834
* Tighten a ARM dag combine condition to avoid an identity transformation, whichEvan Cheng2011-09-281-1/+1
| | | | | | | | ends up introducing a cycle in the DAG. rdar://10196296 llvm-svn: 140733
* PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL ↵David Meyer2011-09-261-1/+3
| | | | | | 2011-06-09-TailCallByVal and 2010-11-04-BigByval llvm-svn: 140516
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-211-26/+26
| | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
* ARM isel bug fix for adds/subs operands.Andrew Trick2011-09-201-16/+57
| | | | | | | | | | | Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the full gamut of CPSR defs/uses including instructins whose "optional" cc_out operand is not really optional. This allowed removal of the hasPostISelHook to simplify the .td files and make the implementation more robust. Fixes rdar://10137436: sqlite3 miscompile llvm-svn: 140134
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