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* fix PR3538 for ARM.Chris Lattner2009-02-121-12/+19
| | | | llvm-svn: 64384
* Eliminate remaining non-DebugLoc version of getTargetNode.Dale Johannesen2009-02-061-1/+3
| | | | llvm-svn: 63951
* get rid of some non-DebugLoc getTargetNode variants.Dale Johannesen2009-02-061-1/+2
| | | | llvm-svn: 63909
* Get rid of one more non-DebugLoc getNode andDale Johannesen2009-02-061-7/+9
| | | | | | | its corresponding getTargetNode. Lots of caller changes. llvm-svn: 63904
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-151-1/+1
| | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. llvm-svn: 62275
* Preliminary ARM debug support based on patch by Mikael of FlexyCore.Evan Cheng2008-12-101-2/+38
| | | | llvm-svn: 60851
* Update a comment.Dan Gohman2008-12-031-3/+4
| | | | llvm-svn: 60484
* Eliminate the ISel priority queue, which used the topological order for aDan Gohman2008-11-051-28/+0
| | | | | | | | | | | | | | | | | | | | | | | | priority function. Instead, just iterate over the AllNodes list, which is already in topological order. This eliminates a fair amount of bookkeeping, and speeds up the isel phase by about 15% on many testcases. The impact on most targets is that AddToISelQueue calls can be simply removed. In the x86 target, there are two additional notable changes. The rule-bending AND+SHIFT optimization in MatchAddress that creates new pre-isel nodes during isel is now a little more verbose, but more robust. Instead of either creating an invalid DAG or creating an invalid topological sort, as it has historically done, it can now just insert the new nodes into the node list at a position where they will be consistent with the topological ordering. Also, the address-matching code has logic that checked to see if a node was "already selected". However, when a node is selected, it has all its uses taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any further visits from MatchAddress. This code is now removed. llvm-svn: 58748
* Have TableGen emit setSubgraphColor calls under control of a -gen-debugDavid Greene2008-10-271-1/+1
| | | | | | | | flag. Then in a debugger developers can set breakpoints at these calls to see waht is about to be selected and what the resulting subgraph looks like. This really helps when debugging instruction selection. llvm-svn: 58278
* Avoid creating two TargetLowering objects for each target.Dan Gohman2008-10-031-3/+1
| | | | | | | | | | | | Instead, just create one, and make sure everything that needs it can access it. Previously most of the SelectionDAGISel subclasses all had their own TargetLowering object, which was redundant with the TargetLowering object in the TargetMachine subclasses, except on Sparc, where SparcTargetMachine didn't have a TargetLowering object. Change Sparc to work more like the other targets here. llvm-svn: 57016
* Cosmetic.Evan Cheng2008-09-181-3/+5
| | | | llvm-svn: 56299
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-21/+27
| | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. llvm-svn: 56159
* erect abstraction boundaries for accessing SDValue members, rename Val -> ↵Gabor Greif2008-08-281-10/+10
| | | | | | Node to reflect semantics llvm-svn: 55504
* disallow direct access to SDValue::ResNo, provide a getter insteadGabor Greif2008-08-261-1/+1
| | | | llvm-svn: 55394
* Move the point at which FastISel taps into the SelectionDAGISelDan Gohman2008-08-231-3/+3
| | | | | | | | | | | | | | | | | | process up to a higher level. This allows FastISel to leverage more of SelectionDAGISel's infastructure, such as updating Machine PHI nodes. Also, implement transitioning from SDISel back to FastISel in the middle of a block, so it's now possible to go back and forth. This allows FastISel to hand individual CallInsts and other complicated things off to SDISel to handle, while handling the rest of the block itself. To help support this, reorganize the SelectionDAG class so that it is allocated once and reused throughout a function, instead of being completely reallocated for each block. llvm-svn: 55219
* Simplify SelectRoot's interface, and factor out some common codeDan Gohman2008-08-211-1/+1
| | | | | | from all targets. llvm-svn: 55124
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-121/+121
| | | | llvm-svn: 54128
* Add a new function, ReplaceAllUsesOfValuesWith, which handles bulkDan Gohman2008-07-171-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | replacement of multiple values. This is slightly more efficient than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically could be optimized even further. However, an important property of this new function is that it handles the case where the source value set and destination value set overlap. This makes it feasible for isel to use SelectNodeTo in many very common cases, which is advantageous because SelectNodeTo avoids a temporary node and it doesn't require CSEMap updates for users of values that don't change position. Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to handle operand lists more efficiently, and to correctly handle a number of corner cases to which its new wider use exposes it. This commit also includes a change to the encoding of post-isel opcodes in SDNodes; now instead of being sandwiched between the target-independent pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel opcodes are now represented as negative values. This makes it possible to test if an opcode is pre-isel or post-isel without having to know the size of the current target's post-isel instruction set. These changes speed up llc overall by 3% and reduce memory usage by 10% on the InstructionCombining.cpp testcase with -fast and -regalloc=local. llvm-svn: 53728
* Add explicit keywords.Dan Gohman2008-07-071-1/+1
| | | | llvm-svn: 53179
* Split scheduling from instruction selection.Evan Cheng2008-06-301-4/+2
| | | | llvm-svn: 52923
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-5/+5
| | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). llvm-svn: 52044
* Dwarf requires variable entries to be in the source order. Right now, since ↵Evan Cheng2008-02-041-1/+0
| | | | | | we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead. llvm-svn: 46724
* explicitly include Compiler.h instead of getting it from tblgen in the ↵Chris Lattner2008-02-031-0/+1
| | | | | | middle of a class. llvm-svn: 46676
* don't do ReplaceUses on a result that doesn't exist.Chris Lattner2008-02-031-2/+4
| | | | llvm-svn: 46673
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+1
| | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. llvm-svn: 46659
* Factor the addressing mode and the load/store VT out of LoadSDNodeDan Gohman2008-01-301-1/+1
| | | | | | | | and StoreSDNode into their common base class LSBaseSDNode. Member functions getLoadedVT and getStoredVT are replaced with the common getMemoryVT to simplify code that will handle both loads and stores. llvm-svn: 46538
* Rename SSARegMap -> MachineRegisterInfo in keeping with the idea Chris Lattner2007-12-311-1/+0
| | | | | | | | | | | | | | that "machine" classes are used to represent the current state of the code being compiled. Given this expanded name, we can start moving other stuff into it. For now, move the UsedPhysRegs and LiveIn/LoveOuts vectors from MachineFunction into it. Update all the clients to match. This also reduces some needless #includes, such as MachineModuleInfo from MachineFunction. llvm-svn: 45467
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | llvm-svn: 45418
* Migrate X86 and ARM from using X86ISD::{,I}DIV and ARMISD::MULHILO{U,S} toDan Gohman2007-10-081-2/+2
| | | | | | | | use ISD::{S,U}DIVREM and ISD::{S,U}MUL_HIO. Move the lowering code associated with these operators into target-independent in LegalizeDAG.cpp and TargetLowering.cpp. llvm-svn: 42762
* Remove clobbersPred. Add an OptionalDefOperand to instructions which have ↵Evan Cheng2007-07-101-12/+14
| | | | | | the 's' bit. llvm-svn: 38501
* Unfortunately we now require C++ code to isel Bcc, conditional moves, etc.Evan Cheng2007-07-051-23/+171
| | | | llvm-svn: 37896
* Add PredicateOperand to all ARM instructions that have the condition field.Evan Cheng2007-05-151-13/+27
| | | | llvm-svn: 37066
* match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.llChris Lattner2007-05-031-0/+1
| | | | llvm-svn: 36660
* Fix naming inconsistencies.Evan Cheng2007-03-191-1/+1
| | | | llvm-svn: 35163
* Special LDR instructions to load from non-pc-relative constantpools. These areEvan Cheng2007-03-191-2/+2
| | | | | | rematerializable. Only used for constant generation for now. llvm-svn: 35162
* AM2 can match 2^n +/- 1. e.g. ldr r3, [r2, r2, lsl #2]Evan Cheng2007-03-131-0/+23
| | | | llvm-svn: 35088
* Get rid of references to iostream.Evan Cheng2007-02-071-1/+0
| | | | llvm-svn: 34009
* Select add FI, c correctly.Evan Cheng2007-02-061-1/+6
| | | | llvm-svn: 33960
* - Store val, [sp, c] must be selected to tSTRsp.Evan Cheng2007-02-061-4/+34
| | | | | | | - If c does not fit in the offset field, materialize sp + c into a register using tADDhirr. llvm-svn: 33944
* Change the operand orders to t_addrmode_s* to make it easier to morphEvan Cheng2007-01-301-15/+15
| | | | | | | instructions that use these address modes to instructions that use t_addrmode_sp. llvm-svn: 33651
* Use PC relative ldr to load from a constantpool in Thumb mode.Evan Cheng2007-01-241-8/+17
| | | | llvm-svn: 33484
* Allow [ fi#c, imm ] as ARM load / store addresses.Evan Cheng2007-01-241-25/+39
| | | | llvm-svn: 33474
* Various Thumb mode load / store isel bug fixes.Evan Cheng2007-01-241-13/+38
| | | | llvm-svn: 33472
* - Reorg Thumb load / store instructions. Combine each rr and ri pair ofEvan Cheng2007-01-231-21/+38
| | | | | | | | | instructions into one (e.g. tLDRrr, tLDRri -> tLDR). - Thumb ldrsb and ldrsh only have the [reg, reg] address format. If the address is not an add, materialize a 0 immediate into a register and use it as the offset field. llvm-svn: 33470
* ARM backend contribution from Apple.Evan Cheng2007-01-191-986/+450
| | | | llvm-svn: 33353
* Build constants using instructions mov/orr or mvn/eor.Lauro Ramos Venancio2007-01-121-20/+74
| | | | llvm-svn: 33141
* Expand SELECT (f32/f64) and FCOPYSIGN (f32/f64).Lauro Ramos Venancio2007-01-041-0/+5
| | | | llvm-svn: 32870
* implement missing comparesRafael Espindola2006-12-311-37/+66
| | | | | | | patch by Lauro bug fixed by me llvm-svn: 32795
* For PR950:Reid Spencer2006-12-311-1/+1
| | | | | | | | | | | | | | | | | | Three changes: 1. Convert signed integer types to signless versions. 2. Implement the @sext and @zext parameter attributes. Previously the type of an function parameter was used to determine whether it should be sign extended or zero extended before the call. This information is now communicated via the function type's parameter attributes. 3. The interface to LowerCallTo had to be changed in order to accommodate the parameter attribute information. Although it would have been convenient to pass in the FunctionType itself, there isn't always one present in the caller. Consequently, a signedness indication for the result type and for each parameter was provided for in the interface to this method. All implementations were changed to make the adjustment necessary. llvm-svn: 32788
* fix commentRafael Espindola2006-12-291-1/+1
| | | | llvm-svn: 32767
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