| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and stores | David Green | 2019-09-17 | 1 | -0/+24 |
| * | [ARM] Invert CSEL predicates if the opposite is a simpler constant to materia... | David Green | 2019-09-03 | 1 | -30/+5 |
| * | [ARM] Fix MVE ldst offset ranges | David Green | 2019-09-03 | 1 | -19/+18 |
| * | Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM | Daniel Sanders | 2019-08-15 | 1 | -2/+2 |
| * | [ARM] Add support for MVE pre and post inc loads and stores | David Green | 2019-08-08 | 1 | -3/+96 |
| * | [ARM][LowOverheadLoops] Fix branch target codegen | Sam Parker | 2019-07-23 | 1 | -6/+19 |
| * | [ARM] WLS/LE Code Generation | Sam Parker | 2019-07-01 | 1 | -0/+10 |
| * | [ARM] Don't reserve R12 on Thumb1 as an emergency spill slot. | Eli Friedman | 2019-06-26 | 1 | -8/+15 |
| * | [ARM] Code-generation infrastructure for MVE. | Simon Tatham | 2019-06-25 | 1 | -0/+32 |
| * | [ARM] DLS/LE low-overhead loop code generation | Sam Parker | 2019-06-25 | 1 | -0/+30 |
| * | [ARM] Replace fp-only-sp and d16 with fp64 and d32. | Simon Tatham | 2019-05-28 | 1 | -3/+3 |
| * | [ARM][FIX] Add missing f16.lane.vldN/vstN lowering | Diogo N. Sampaio | 2019-04-23 | 1 | -0/+2 |
| * | [ARM] [FIX] Add missing f16 vector operations lowering | Diogo N. Sampaio | 2019-04-10 | 1 | -1/+4 |
| * | [ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1. | Eli Friedman | 2019-03-20 | 1 | -13/+47 |
| * | [ARM] Fix selection of VLDR.16 instruction with imm offset | Oliver Stannard | 2019-03-04 | 1 | -10/+5 |
| * | Implementation of asm-goto support in LLVM | Craig Topper | 2019-02-08 | 1 | -1/+2 |
| * | [ARM] Add OptMinSize to ARMSubtarget | Sam Parker | 2019-02-08 | 1 | -1/+1 |
| * | [ARM] Thumb2: ConstantMaterializationCost | Sjoerd Meijer | 2019-01-31 | 1 | -2/+4 |
| * | [ARM] Use sub for negative offset load/store in thumb1 | David Green | 2019-01-29 | 1 | -2/+30 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [ARM] FP16: support vld1.16 for vector loads with post-increment | Sjoerd Meijer | 2018-12-03 | 1 | -0/+2 |
| * | [SDAG] Remove the reliance on MI's allocation strategy for | Chandler Carruth | 2018-08-14 | 1 | -31/+22 |
| * | [ARM] Adjust AND immediates to make them cheaper to select. | Eli Friedman | 2018-08-10 | 1 | -0/+5 |
| * | [ARM] FP16: codegen support for VTRN | Sjoerd Meijer | 2018-08-09 | 1 | -0/+2 |
| * | [ARM] FP16: support vector zip and unzip | Sjoerd Meijer | 2018-08-03 | 1 | -0/+4 |
| * | Remove trailing space | Fangrui Song | 2018-07-30 | 1 | -4/+4 |
| * | [ARM] Assert that ARMDAGToDAGISel creates valid UBFX/SBFX nodes. | Eli Friedman | 2018-06-28 | 1 | -0/+4 |
| * | [NEON] Support vldNq intrinsics in AArch32 (LLVM part) | Ivan A. Kosarev | 2018-06-27 | 1 | -55/+145 |
| * | ARM: convert ORR instructions to ADD where possible on Thumb. | Tim Northover | 2018-06-20 | 1 | -0/+10 |
| * | [NEON] Support VST1xN intrinsics in AArch32 mode (LLVM part) | Ivan A. Kosarev | 2018-06-10 | 1 | -3/+46 |
| * | [ARM] Allow CMPZ transforms even if the input has multiple uses. | Eli Friedman | 2018-06-08 | 1 | -1/+1 |
| * | [NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part) | Ivan A. Kosarev | 2018-06-02 | 1 | -3/+46 |
| * | Revert r333819 "[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)" | Ivan A. Kosarev | 2018-06-02 | 1 | -46/+3 |
| * | [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part) | Ivan A. Kosarev | 2018-06-02 | 1 | -3/+46 |
| * | Remove \brief commands from doxygen comments. | Adrian Prantl | 2018-05-01 | 1 | -8/+8 |
| * | [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172" | Nirav Dave | 2018-03-19 | 1 | -1/+1 |
| * | [ARM] Support for v4f16 and v8f16 vectors | Sjoerd Meijer | 2018-03-19 | 1 | -0/+2 |
| * | Revert "[DAG, X86] Revert r327197 "Revert r327170, r327171, r327172"" | Nirav Dave | 2018-03-17 | 1 | -1/+1 |
| * | [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172" | Nirav Dave | 2018-03-17 | 1 | -1/+1 |
| * | Revert: r327172 "Correct load-op-store cycle detection analysis" | Nirav Dave | 2018-03-10 | 1 | -1/+1 |
| * | [DAG] Enforce stricter NodeId invariant during Instruction selection | Nirav Dave | 2018-03-09 | 1 | -1/+1 |
| * | [ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WB | Florian Hahn | 2018-03-02 | 1 | -16/+19 |
| * | [ARM] Armv8.2-A FP16 code generation (part 1/3) | Sjoerd Meijer | 2018-01-26 | 1 | -10/+39 |
| * | [ARM] Fix erroneous availability of SMMLS for Armv7-M | Andre Vieira | 2018-01-12 | 1 | -1/+1 |
| * | Fix a bunch more layering of CodeGen headers that are in Target | David Blaikie | 2017-11-17 | 1 | -2/+2 |
| * | [ARM] Split Arm jump table branch into i12 and rs suffixed versions | Momchil Velikov | 2017-11-15 | 1 | -167/+0 |
| * | [ARM] Tidy up banked registers encoding | Javed Absar | 2017-08-03 | 1 | -35/+4 |
| * | [ARM] Unify handling of M-Class system registers | Javed Absar | 2017-07-19 | 1 | -89/+11 |
| * | [ARM] Allow rematerialization of ARM Thumb literal pool loads | Sam Parker | 2017-07-14 | 1 | -3/+17 |
| * | ARM: avoid handing a deleted node back to TableGen during ISel. | Tim Northover | 2017-05-02 | 1 | -0/+4 |
