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path: root/llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
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* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2020-02-081-49/+0
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2020-01-071-0/+49
* [SelectionDAG] Disallow indirect "i" constraintFangrui Song2019-12-291-4/+0
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2019-12-201-49/+0
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2019-12-191-0/+49
* [ARM][MVE] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=Off builds after...Fangrui Song2019-12-131-3/+4
* [ARM][MVE] Add vector reduction intrinsics with two vector operandsMikhail Maltsev2019-12-131-0/+147
* [ARM][MVE] Add intrinsics for more immediate shifts.Simon Tatham2019-12-131-0/+13
* [IR] Split out target specific intrinsic enums into separate headersReid Kleckner2019-12-111-0/+1
* [ARM][MVE] Refactor complex vector intrinsics [NFCI]Mikhail Maltsev2019-12-101-177/+0
* [ARM][MVE] Add complex vector intrinsicsMikhail Maltsev2019-12-091-0/+178
* [Codegen][ARM] Add addressing modes from masked loads and storesDavid Green2019-11-261-31/+87
* [ARM,MVE] Add intrinsics for scalar shifts.Simon Tatham2019-11-191-4/+34
* [ARM] Add IR intrinsics for MVE VLD[24] and VST[24].Simon Tatham2019-10-241-0/+74
* [ARM] Add some sample IR MVE intrinsics with C++ isel.Simon Tatham2019-10-241-0/+173
* [ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and storesDavid Green2019-09-171-0/+24
* [ARM] Invert CSEL predicates if the opposite is a simpler constant to materia...David Green2019-09-031-30/+5
* [ARM] Fix MVE ldst offset rangesDavid Green2019-09-031-19/+18
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-2/+2
* [ARM] Add support for MVE pre and post inc loads and storesDavid Green2019-08-081-3/+96
* [ARM][LowOverheadLoops] Fix branch target codegenSam Parker2019-07-231-6/+19
* [ARM] WLS/LE Code GenerationSam Parker2019-07-011-0/+10
* [ARM] Don't reserve R12 on Thumb1 as an emergency spill slot.Eli Friedman2019-06-261-8/+15
* [ARM] Code-generation infrastructure for MVE.Simon Tatham2019-06-251-0/+32
* [ARM] DLS/LE low-overhead loop code generationSam Parker2019-06-251-0/+30
* [ARM] Replace fp-only-sp and d16 with fp64 and d32.Simon Tatham2019-05-281-3/+3
* [ARM][FIX] Add missing f16.lane.vldN/vstN loweringDiogo N. Sampaio2019-04-231-0/+2
* [ARM] [FIX] Add missing f16 vector operations loweringDiogo N. Sampaio2019-04-101-1/+4
* [ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1.Eli Friedman2019-03-201-13/+47
* [ARM] Fix selection of VLDR.16 instruction with imm offsetOliver Stannard2019-03-041-10/+5
* Implementation of asm-goto support in LLVMCraig Topper2019-02-081-1/+2
* [ARM] Add OptMinSize to ARMSubtargetSam Parker2019-02-081-1/+1
* [ARM] Thumb2: ConstantMaterializationCostSjoerd Meijer2019-01-311-2/+4
* [ARM] Use sub for negative offset load/store in thumb1David Green2019-01-291-2/+30
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [ARM] FP16: support vld1.16 for vector loads with post-incrementSjoerd Meijer2018-12-031-0/+2
* [SDAG] Remove the reliance on MI's allocation strategy forChandler Carruth2018-08-141-31/+22
* [ARM] Adjust AND immediates to make them cheaper to select.Eli Friedman2018-08-101-0/+5
* [ARM] FP16: codegen support for VTRNSjoerd Meijer2018-08-091-0/+2
* [ARM] FP16: support vector zip and unzipSjoerd Meijer2018-08-031-0/+4
* Remove trailing spaceFangrui Song2018-07-301-4/+4
* [ARM] Assert that ARMDAGToDAGISel creates valid UBFX/SBFX nodes.Eli Friedman2018-06-281-0/+4
* [NEON] Support vldNq intrinsics in AArch32 (LLVM part)Ivan A. Kosarev2018-06-271-55/+145
* ARM: convert ORR instructions to ADD where possible on Thumb.Tim Northover2018-06-201-0/+10
* [NEON] Support VST1xN intrinsics in AArch32 mode (LLVM part)Ivan A. Kosarev2018-06-101-3/+46
* [ARM] Allow CMPZ transforms even if the input has multiple uses.Eli Friedman2018-06-081-1/+1
* [NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part)Ivan A. Kosarev2018-06-021-3/+46
* Revert r333819 "[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)"Ivan A. Kosarev2018-06-021-46/+3
* [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)Ivan A. Kosarev2018-06-021-3/+46
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-8/+8
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