summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMFixupKinds.h
Commit message (Collapse)AuthorAgeFilesLines
* Sink ARM mc routines into MCTargetDesc.Evan Cheng2011-07-231-97/+0
| | | | llvm-svn: 135825
* Fix comment.Eric Christopher2011-05-271-1/+1
| | | | llvm-svn: 132178
* Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.Jason W Kim2011-02-041-3/+6
| | | | | | | | | | | | | | | | (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895
* Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.Evan Cheng2011-01-141-1/+4
| | | | | | | | - Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first. - Added support for Thumb2 :lower16: and :upper16: fix up. - Added :upper16: and :lower16: relocation support to mach-o object writer. llvm-svn: 123424
* Added clarifying commentJason W Kim2011-01-121-0/+2
| | | | llvm-svn: 123341
* 1. Support ELF pcrel relocations for movw/movt:Jason W Kim2011-01-121-0/+5
| | | | | | | | R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC. 2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum. 3. Add support for 3 new elf section types (no-ops) llvm-svn: 123294
* Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff forBill Wendling2010-12-161-3/+0
| | | | | | it. I.e., it was always an immediate value. llvm-svn: 121932
* Add fixups for Thumb LDR/STR instructions.Bill Wendling2010-12-151-0/+3
| | | | llvm-svn: 121858
* Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach2010-12-141-0/+4
| | | | llvm-svn: 121798
* Fix comment.Bill Wendling2010-12-141-1/+1
| | | | llvm-svn: 121797
* trailing whitespaceJim Grosbach2010-12-141-4/+4
| | | | llvm-svn: 121792
* Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering ↵Owen Anderson2010-12-141-0/+3
| | | | | | | | much later, which makes the entire process cleaner. llvm-svn: 121735
* Revert r121721, which broke buildbots.Owen Anderson2010-12-131-3/+0
| | | | llvm-svn: 121726
* Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. ↵Owen Anderson2010-12-131-0/+3
| | | | | | | | Provide correct fixups for Thumb2 ADR, which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup. llvm-svn: 121721
* In Thumb2, direct branches can be encoded as either a "short" conditional ↵Owen Anderson2010-12-131-3/+6
| | | | | | | | | | branch with a null predicate, or as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise equivalence, provide encoding and fixup support for it. llvm-svn: 121710
* Thumb unconditional branch binary encoding. rdar://8754994Jim Grosbach2010-12-101-0/+3
| | | | llvm-svn: 121496
* Thumb conditional branch binary encodings. rdar://8745367Jim Grosbach2010-12-101-0/+3
| | | | llvm-svn: 121493
* Rename CB/CBZ specific fixup accordingly.Jim Grosbach2010-12-091-2/+2
| | | | llvm-svn: 121404
* Fix Thumb2 fixups for ldr.Owen Anderson2010-12-091-0/+5
| | | | llvm-svn: 121350
* The BLX instruction is encoded differently than the BL, because why not? InBill Wendling2010-12-091-1/+4
| | | | | | | | | | particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0' always. Going through the BL fixup encoding was trashing the "bit 0 is '0'" invariant. Attempt to get the encoding at slightly more correct with this. llvm-svn: 121336
* Fix Thumb2 BCC encoding and fixups.Owen Anderson2010-12-091-1/+4
| | | | llvm-svn: 121329
* Support the "target" encodings for the CB[N]Z instructions.Bill Wendling2010-12-081-0/+4
| | | | llvm-svn: 121308
* Add support for loading from a constant pool.Bill Wendling2010-12-081-0/+3
| | | | llvm-svn: 121226
* VLDR fixups need special handling under Thumb. While the encoding is the same,Owen Anderson2010-12-081-1/+4
| | | | | | the order of the bytes in the data stream is flipped around. llvm-svn: 121215
* Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach2010-12-061-1/+3
| | | | llvm-svn: 121072
* Add support for binary encoding of ARM 'adr' instructions referencing constantJim Grosbach2010-12-021-2/+6
| | | | | | pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291. llvm-svn: 120635
* Add correct encodings for STRD and LDRD, including fixup support. ↵Owen Anderson2010-12-011-4/+4
| | | | | | Additionally, update these to unified syntax. llvm-svn: 120589
* 10 bits, not 12.Jim Grosbach2010-12-011-2/+2
| | | | llvm-svn: 120584
* Fix .o emission of ARM movt/movw. MCSymbolRefExpr::VK_ARM_(HI||LO)16 for the ↵Jason W Kim2010-11-181-0/+6
| | | | | | | | | .o path now works for ARM. Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired. Existing tests cover this update. llvm-svn: 119760
* Encoding of destination fixup for ARM branch and conditional branchJim Grosbach2010-11-111-1/+8
| | | | | | instructions. llvm-svn: 118801
* Add ARM fixup info for load/store label references. Probably will need a bit ofJim Grosbach2010-11-041-0/+28
tweaking when we start using it for object file emission or JIT, but it's a start. llvm-svn: 118221
OpenPOWER on IntegriCloud