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path: root/llvm/lib/Target/ARM/ARMFastISel.cpp
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* Recommit this change and remove the failing part of the test - it didn'tEric Christopher2010-11-151-4/+5
| | | | | | | pass in the first place and was masked by earlier failures not warning and aborting the block. llvm-svn: 119184
* Temporarily revert this.Eric Christopher2010-11-121-5/+4
| | | | llvm-svn: 118946
* Make this happen for ARM like x86. Don't entirely bail out whenEric Christopher2010-11-121-4/+5
| | | | | | | an address is in a different block, get it into a register and go from there. llvm-svn: 118936
* Fix up a few more spots of addrmode2 (or not) changes that wereEric Christopher2010-11-121-6/+12
| | | | | | | | missed. Update some comments accordingly. Fixes rdar://8652289 llvm-svn: 118888
* Trailing whitespace.Jim Grosbach2010-11-091-6/+6
| | | | llvm-svn: 118606
* Make sure we have movw on the target before using it.Eric Christopher2010-11-061-1/+1
| | | | | | Fixes 8559. llvm-svn: 118333
* In the calling convention logic, ValVT is always a legal type,Duncan Sands2010-11-041-1/+1
| | | | | | | and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. llvm-svn: 118245
* Optimize generated code for integer materialization a bit.Eric Christopher2010-11-031-1/+13
| | | | llvm-svn: 118192
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-031-7/+6
| | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. llvm-svn: 118169
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-031-36/+36
| | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. llvm-svn: 118167
* Invert these branches by default, it makes assembly comparisons a littleEric Christopher2010-11-031-2/+2
| | | | | | easier to read. llvm-svn: 118148
* Make sure we're only storing a single bit here.Eric Christopher2010-11-021-2/+9
| | | | llvm-svn: 118126
* Remove an assert - it's possible to be hit, and we just want to avoidEric Christopher2010-11-021-1/+1
| | | | | | handling those cases for now. llvm-svn: 117996
* WhitespeaceEric Christopher2010-11-021-1/+1
| | | | llvm-svn: 117995
* No really, no thumb1 for arm fast isel. Also add an informative comment asEric Christopher2010-11-021-3/+7
| | | | | | to what someone would need to do to support thumb1. llvm-svn: 117994
* Make sure we have a legal type (and simple) before continuing.Eric Christopher2010-10-301-1/+4
| | | | llvm-svn: 117848
* Handle comparison values we already have - this fixes the consumer-typesetEric Christopher2010-10-291-4/+65
| | | | | | failure for llvm-gcc on arm fast isel. llvm-svn: 117710
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-5/+8
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
* Trailing whitespaceJim Grosbach2010-10-271-17/+17
| | | | llvm-svn: 117496
* Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing onJim Grosbach2010-10-271-3/+1
| | | | | | rdar://8477752. llvm-svn: 117419
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-10/+5
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* Move rejection of NEON parameters earlier in fast isel call processing,Eric Christopher2010-10-231-3/+4
| | | | | | note that we can actually handle some f64 arguments. llvm-svn: 117209
* Silence compiler warnings.Evan Cheng2010-10-221-1/+5
| | | | llvm-svn: 117128
* Add some basic ret instruction support to arm fast-isel.Eric Christopher2010-10-221-0/+66
| | | | llvm-svn: 117085
* These don't need to be virtual.Eric Christopher2010-10-211-13/+13
| | | | llvm-svn: 117068
* Handle storing args to the stack for calls.Eric Christopher2010-10-211-4/+6
| | | | llvm-svn: 117055
* More load/store refactoring, call reg+offset simplification from withinEric Christopher2010-10-211-28/+36
| | | | | | | | the emitter to handle the addresses. Only simplify the offset if we need to - also fix bug where in addrmode 5 we weren't dividing the offset by 4, which showed up due to not always lowering. llvm-svn: 117051
* Custom lower f64 args passed in integer registers.Eric Christopher2010-10-211-0/+15
| | | | llvm-svn: 116977
* Fix a TODO by removing some unnecesary copies.Eric Christopher2010-10-201-13/+5
| | | | llvm-svn: 116915
* Revert r116220 - thus turning arm fast isel back on by default.Eric Christopher2010-10-181-3/+3
| | | | llvm-svn: 116762
* Remove the check for invalid calling conventions. Testing shows that they'reEric Christopher2010-10-181-4/+1
| | | | | | working just fine. llvm-svn: 116698
* Lift arg promotion from the X86 backend. This should be unified at some point.Eric Christopher2010-10-181-3/+57
| | | | llvm-svn: 116694
* Now that we handle all allocas via a non-SP reg offset remove all of theEric Christopher2010-10-171-79/+39
| | | | | | special case handling for ARM::SP. llvm-svn: 116688
* Allow more load types to be materialized through the allocas.Eric Christopher2010-10-171-1/+1
| | | | llvm-svn: 116683
* Optimize GEP off of intermediate allocas.Eric Christopher2010-10-171-14/+46
| | | | llvm-svn: 116681
* Fix comment.Eric Christopher2010-10-171-1/+1
| | | | llvm-svn: 116680
* Turn on AddOperator folding in GEP.Eric Christopher2010-10-171-1/+1
| | | | llvm-svn: 116679
* Use the i12 immediate versions of the load instructions - they're handledEric Christopher2010-10-171-6/+6
| | | | | | more in the post-passes. llvm-svn: 116678
* Fix some funky formatting that got through.Eric Christopher2010-10-161-1/+3
| | | | llvm-svn: 116653
* Make sure offset is 0 for load/store register to the stack call.Eric Christopher2010-10-151-2/+2
| | | | llvm-svn: 116640
* Fix else if -> if in store machinery.Eric Christopher2010-10-151-1/+1
| | | | llvm-svn: 116628
* Refactor ARM fast-isel reg + offset to be a base + offset.Eric Christopher2010-10-151-40/+45
| | | | llvm-svn: 116622
* Expand GEP handling for constant offsets.Eric Christopher2010-10-151-23/+44
| | | | llvm-svn: 116594
* Handle more complex GEP based loads and add a few TODOs to deal withEric Christopher2010-10-141-10/+50
| | | | | | GEP + alloca. llvm-svn: 116474
* A few 80 column fixes.Jim Grosbach2010-10-131-1/+1
| | | | llvm-svn: 116451
* Update comment.Eric Christopher2010-10-131-1/+2
| | | | llvm-svn: 116438
* Start handling more global variables.Eric Christopher2010-10-131-2/+5
| | | | llvm-svn: 116401
* Fix thinko in arm fast isel alloca rewrite.Eric Christopher2010-10-121-1/+1
| | | | llvm-svn: 116339
* Rework alloca handling so that we can load or store from castedEric Christopher2010-10-121-63/+29
| | | | | | | | address that we've looked through. Fixes compilation problems in tramp3d from earlier patch. llvm-svn: 116296
* Handle a wider arrangement of loads.Eric Christopher2010-10-121-0/+16
| | | | llvm-svn: 116284
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