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* Reinstate "Nuke the old JIT."Eric Christopher2014-09-021-1910/+0
| | | | | | | | Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reinstates commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 216982
* Temporarily Revert "Nuke the old JIT." as it's not quite ready toEric Christopher2014-08-071-0/+1910
| | | | | | | | | | | be deleted. This will be reapplied as soon as possible and before the 3.6 branch date at any rate. Approved by Jim Grosbach, Lang Hames, Rafael Espindola. This reverts commits r215111, 215115, 215116, 215117, 215136. llvm-svn: 215154
* Nuke the old JIT.Rafael Espindola2014-08-071-1910/+0
| | | | | | | | | I am sure we will be finding bits and pieces of dead code for years to come, but this is a good start. Thanks to Lang Hames for making MCJIT a good replacement! llvm-svn: 215111
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-10/+11
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-181-0/+1
| | | | | | | | | This required untangling a mess of headers that included around. This a recommit of r210953 with a fix for the removed accessor for JITInfo. llvm-svn: 211233
* Temporarily revert r210953 in an attempt to bring the ARM buildbotsEric Christopher2014-06-151-1/+0
| | | | | | back. llvm-svn: 210996
* Move ARMJITInfo off of the TargetMachine and down onto the subtarget.Eric Christopher2014-06-131-0/+1
| | | | | | This required untangling a mess of headers that included around. llvm-svn: 210953
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-3/+3
| | | | llvm-svn: 207197
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-1/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* remove a bunch of unused private methodsNuno Lopes2014-03-231-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | found with a smarter version of -Wunused-member-function that I'm playwing with. Appologies in advance if I removed someone's WIP code. include/llvm/CodeGen/MachineSSAUpdater.h | 1 include/llvm/IR/DebugInfo.h | 3 lib/CodeGen/MachineSSAUpdater.cpp | 10 -- lib/CodeGen/PostRASchedulerList.cpp | 1 lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 -- lib/IR/DebugInfo.cpp | 12 -- lib/MC/MCAsmStreamer.cpp | 2 lib/Support/YAMLParser.cpp | 39 --------- lib/TableGen/TGParser.cpp | 16 --- lib/TableGen/TGParser.h | 1 lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 9 -- lib/Target/ARM/ARMCodeEmitter.cpp | 12 -- lib/Target/ARM/ARMFastISel.cpp | 84 -------------------- lib/Target/Mips/MipsCodeEmitter.cpp | 11 -- lib/Target/Mips/MipsConstantIslandPass.cpp | 12 -- lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp | 21 ----- lib/Target/NVPTX/NVPTXISelDAGToDAG.h | 2 lib/Target/PowerPC/PPCFastISel.cpp | 1 lib/Transforms/Instrumentation/AddressSanitizer.cpp | 2 lib/Transforms/Instrumentation/BoundsChecking.cpp | 2 lib/Transforms/Instrumentation/MemorySanitizer.cpp | 1 lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 8 - lib/Transforms/Scalar/SCCP.cpp | 1 utils/TableGen/CodeEmitterGen.cpp | 2 24 files changed, 2 insertions(+), 261 deletions(-) llvm-svn: 204560
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-3/+3
| | | | | | class. llvm-svn: 203433
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. llvm-svn: 203204
* [ARMv8] Add support for the NEON instructions vmaxnm/vminnm.Joey Gouly2013-07-171-0/+2
| | | | | | | This adds a new class for non-predicable NEON instructions and a new DecoderNamespace for v8 NEON instructions. llvm-svn: 186504
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-241-2/+2
| | | | llvm-svn: 182680
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-3/+3
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
* Cleanup compiler warnings on discarding type qualifiers in casts. Switch to ↵Benjamin Kramer2012-12-211-5/+9
| | | | | | | | | | C++ style casts. Patch by Saleem Abdulrasool! Differential Revision: http://llvm-reviews.chandlerc.com/D204 llvm-svn: 170917
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-6/+6
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Move TargetData to DataLayout.Micah Villmow2012-10-081-3/+3
| | | | llvm-svn: 165402
* Add a getName function to MachineFunction. Use it in places that previously ↵Craig Topper2012-08-221-1/+1
| | | | | | did getFunction()->getName(). Remove includes of Function.h that are no longer needed. llvm-svn: 162347
* Remove getARMRegisterNumbering and replace with calls intoEric Christopher2012-08-091-29/+41
| | | | | | | | | | | the register info for getEncodingValue. This builds on the small patch of yesterday to set HWEncoding in the register file. One (deprecated) use was turned into a hard number to avoid needing register info in the old JIT. llvm-svn: 161628
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-3/+3
| | | | | | since they are equivalent. llvm-svn: 155188
* Deduplicate ARM call-related instructions.Jakob Stoklund Olesen2012-04-061-3/+1
| | | | | | | | We had special instructions for iOS because r9 is call-clobbered, but that is represented dynamically by the register mask operands now, so there is no need for the pseudo-instructions. llvm-svn: 154144
* Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.Craig Topper2012-03-251-6/+6
| | | | llvm-svn: 153421
* ARM BL/BLX instruction fixups should use relocations.Jim Grosbach2012-02-271-0/+2
| | | | | | | | | | | | | We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 llvm-svn: 151571
* Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson2012-01-241-1/+1
| | | | | | accomodate every target I can think of offhand. llvm-svn: 148833
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-3/+0
| | | | llvm-svn: 148578
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-1/+1
| | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs llvm-svn: 145975
* Use the new ARMConstantPoolSymbol class to handle external symbols.Bill Wendling2011-10-011-2/+3
| | | | llvm-svn: 140939
* Switch over to using ARMConstantPoolConstant for global variables, functions,Bill Wendling2011-10-011-1/+1
| | | | | | and block addresses. llvm-svn: 140936
* Zap some junk from the ARM instruction descriptions.Eli Friedman2011-09-131-2/+0
| | | | llvm-svn: 139575
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-0/+2
| | | | llvm-svn: 139381
* Thumb2 assembly parsing and encoding for LDRD(immediate).Jim Grosbach2011-09-081-0/+2
| | | | | | Refactor operand handling for STRD as well. Tests for that forthcoming. llvm-svn: 139322
* Tidy up. Formatting.Jim Grosbach2011-09-021-4/+4
| | | | llvm-svn: 139024
* Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson2011-08-261-0/+2
| | | | | | decoding bug this uncovered. llvm-svn: 138675
* ARM clean up the imm_sr operand class representation.Jim Grosbach2011-08-171-2/+0
| | | | | | | | | Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. llvm-svn: 137879
* Fix encodings for Thumb ASR and LSR immediate operands. They encode the ↵Owen Anderson2011-08-081-0/+2
| | | | | | range 1-32, with 32 encoded as 0. llvm-svn: 137062
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
* ARM parsing and encoding of SBFX and UBFX.Jim Grosbach2011-07-271-2/+0
| | | | | | | | | Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. llvm-svn: 136264
* ARM cleanup of rot_imm encoding.Jim Grosbach2011-07-261-2/+0
| | | | | | | | Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. llvm-svn: 136152
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-1/+3
| | | | | | necessitates a lot of changes to related bits. llvm-svn: 135722
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. llvm-svn: 135636
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-75/+75
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Fix ssat and ssat16 encodings for ARM and Thumb. The bit position valueBruno Cardoso Lopes2011-05-311-0/+2
| | | | | | | must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. llvm-svn: 132324
* Fixed MC encoding for index_align for VLD1/VST1 (single element from one ↵Mon P Wang2011-05-091-0/+3
| | | | | | lane) for size 32 llvm-svn: 131085
* Fix the non-MC encoding of pkhbt and pkhtb.Eric Christopher2011-05-071-0/+6
| | | | | | Patch by Stephen Hines. llvm-svn: 131045
* Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling2011-03-071-3/+5
| | | | | | | | expand the testing of the narrowing shift right instructions. No functionality change. llvm-svn: 127193
* PR8053: Fix encoding of S bit in some ARM instructions.Bob Wilson2011-03-031-1/+1
| | | | | | Patch by Zonr Chang! llvm-svn: 126967
* Narrow right shifts need to encode their immediates differently from a normalBill Wendling2011-03-011-0/+7
| | | | | | | | | | shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> llvm-svn: 126723
* Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.Jason W Kim2011-02-041-0/+2
| | | | | | | | | | | | | | | | (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td llvm-svn: 124895
* Add support for parsing and encoding ARM's official syntax for the BFI ↵Bruno Cardoso Lopes2011-01-181-0/+2
| | | | | | instruction llvm-svn: 123770
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