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* 80 column fix.Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117741
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-291-1/+1
| | | | | | encoder functions. llvm-svn: 117738
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-2/+3
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
* Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson2010-10-271-0/+2
| | | | | | | | encoding for specifying fractional bits for fixed point conversions. llvm-svn: 117501
* JIT imm12 encoding for constant pool entry references.Jim Grosbach2010-10-271-0/+4
| | | | llvm-svn: 117483
* ARM JIT fix for LDRi12 and company.Jim Grosbach2010-10-271-4/+17
| | | | llvm-svn: 117478
* The new LDR* instruction patterns should handle the necessary encoding ofJim Grosbach2010-10-271-0/+7
| | | | | | | operands in the TableGen'erated bits, so we don't need to do the additional magic explicitly. llvm-svn: 117461
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-0/+2
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* fix memory-layout assumption which only holds on little-endian systemsGabor Greif2010-10-221-1/+1
| | | | llvm-svn: 117176
* ARM Binary encoding information for BFC/BFI instructions.Jim Grosbach2010-10-211-0/+2
| | | | llvm-svn: 117072
* Add encodings for movement between ARM core registers and single-precisionBill Wendling2010-10-201-1/+1
| | | | | | registers. llvm-svn: 116961
* ARMCodeEmitter::emitMiscInstruction is dead. Long liveBill Wendling2010-10-151-45/+1
| | | | | | ARMCodeEmitter::emitMiscInstruction! llvm-svn: 116644
* ARM mode encoding information for UBFX and SBFX instructions.Jim Grosbach2010-10-151-0/+2
| | | | llvm-svn: 116588
* Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'Jim Grosbach2010-10-141-2/+2
| | | | | | pseudonym. llvm-svn: 116512
* Add encoding for 'fmstat'.Bill Wendling2010-10-141-4/+0
| | | | llvm-svn: 116466
* - Add encodings for multiply add/subtract instructions in all their glory.Bill Wendling2010-10-141-9/+1
| | | | | | | - Add missing patterns for some multiply add/subtract instructions. - Add encodings for VMRS and VMSR. llvm-svn: 116464
* Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.Jim Grosbach2010-10-131-0/+2
| | | | llvm-svn: 116421
* Add the rest of the ARM so_reg encoding options (register shifted register)Jim Grosbach2010-10-121-0/+2
| | | | | | | and move to a custom operand encoder. Remove the last of the special handling stuff from ARMMCCodeEmitter::EncodeInstruction. llvm-svn: 116377
* Move the ARM so_imm encoding into a custom operand encoder and remove theJim Grosbach2010-10-121-0/+2
| | | | | | | explicit handling of the instructions referencing it from the MC code emitter. llvm-svn: 116367
* Add custom encoder for the 's' bit denoting whether an ARM arithmeticJim Grosbach2010-10-121-0/+11
| | | | | | | instruction should set the processor status flags or not. Remove the now unnecessary special handling for the bit from the MCCodeEmitter. llvm-svn: 116360
* Reapply 116059, this time without the fatfingered pasto at the top.Jim Grosbach2010-10-081-13/+17
| | | | | | ''const'ify getMachineOpValue() and associated helpers.' llvm-svn: 116067
* Reverting 116059. Bots are unhappy with it.Jim Grosbach2010-10-081-18/+14
| | | | llvm-svn: 116064
* 'const'ify getMachineOpValue() and associated helpers.Jim Grosbach2010-10-081-14/+18
| | | | llvm-svn: 116059
* Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.Jim Grosbach2010-10-081-1/+1
| | | | llvm-svn: 116018
* move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helperJim Grosbach2010-09-151-29/+22
| | | | | | | | | functions in ARMBaseInfo.h so it can be used in the MC library as well. For anything bigger than this, we may want a means to have a small support library for shared helper functions like this. Cross that bridge when we come to it. llvm-svn: 114016
* Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. CheckJim Grosbach2010-09-151-6/+6
| | | | | | if the register is a member of the SPR register class directly instead. llvm-svn: 114012
* zap dead code.Chris Lattner2010-09-041-4/+0
| | | | llvm-svn: 113073
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-271-2/+2
| | | | | | | | | | | | | | | | | | | all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. llvm-svn: 112322
* Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoidBob Wilson2010-08-171-0/+5
| | | | | | | printing "lsl #0". This fixes the remaining parts of pr7792. Make corresponding changes for encoding/decoding these instructions. llvm-svn: 111251
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-111-5/+6
| | | | | | instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-111-0/+45
| | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. llvm-svn: 110754
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
* ARMv4 JIT forgets to set the lr register when making a indirect function ↵Xerxes Ranby2010-07-221-0/+13
| | | | | | call. Fixes PR7608 llvm-svn: 109125
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-1/+1
| | | | | | thus is a much more meaningful name. llvm-svn: 108563
* Add support for encoding VDUP (ARM core register) instructions.Bob Wilson2010-06-291-0/+17
| | | | llvm-svn: 107201
* Add support for encoding NEON VMOV (from core register to scalar) instructions.Bob Wilson2010-06-291-6/+19
| | | | | | | The encoding is the same as VMOV (from scalar to core register) except that the operands are in different places. llvm-svn: 107167
* Fix Thumb encoding of VMOV (scalar to ARM core register). The encoding isBob Wilson2010-06-291-1/+1
| | | | | | the same as ARM except that the condition code field is always set to ARMCC::AL. llvm-svn: 107107
* Make the ARMCodeEmitter identify Thumb functions via ARMFunctionInfo insteadBob Wilson2010-06-281-5/+7
| | | | | | of the Subtarget. llvm-svn: 107086
* Refactor encoding function for NEON 1-register with modified immediate format.Bob Wilson2010-06-281-5/+1
| | | | llvm-svn: 107070
* Support Thumb mode encoding of NEON instructions.Bob Wilson2010-06-281-0/+15
| | | | llvm-svn: 107068
* Add support for encoding NEON VMOV (from scalar to core register) instructions.Bob Wilson2010-06-261-0/+33
| | | | llvm-svn: 106938
* Add support for encoding 3-register NEON instructions, and fixBob Wilson2010-06-251-3/+36
| | | | | | emitNEON2RegInstruction's handling of 2-address operands. llvm-svn: 106900
* Add support for encoding 2-register NEON instructions.Bob Wilson2010-06-251-3/+25
| | | | llvm-svn: 106891
* Use pre-increment instead of post-increment when the result is not used.Dan Gohman2010-06-221-1/+1
| | | | llvm-svn: 106542
* Add instruction encoding for the Neon VMOV immediate instruction. This changesBob Wilson2010-06-111-0/+34
| | | | | | | | | | | the machine instruction representation of the immediate value to be encoded into an integer with similar fields as the actual VMOV instruction. This makes things easier for the disassembler, since it can just stuff the bits into the immediate operand, but harder for the asm printer since it has to decode the value to be printed. Testcase for the encoding will follow later when MC has more support for ARM. llvm-svn: 105836
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-021-1/+2
| | | | llvm-svn: 105350
* Coding style change (Adding 1 missing space.)Shih-wei Liao2010-05-261-1/+1
| | | | llvm-svn: 104670
* Adding the missing implementation for ARM::SBFX and ARM::UBFX.Shih-wei Liao2010-05-261-1/+13
| | | | | | Fixing http://llvm.org/bugs/show_bug.cgi?id=7225. llvm-svn: 104667
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