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path: root/llvm/lib/Target/ARM/ARMCodeEmitter.cpp
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* Eliminate ARM::MOVi2pieces. Just use MOVi32imm and expand it to either ↵Evan Cheng2010-11-121-5/+5
| | | | | | movi+orr or movw+movt depending on the subtarget. llvm-svn: 118938
* First stab at providing correct Thumb2 encodings, start with adc.Owen Anderson2010-11-121-0/+4
| | | | llvm-svn: 118924
* Fill out support for Thumb2 encodings of NEON instructions.Owen Anderson2010-11-111-0/+2
| | | | llvm-svn: 118854
* Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].Owen Anderson2010-11-111-0/+2
| | | | llvm-svn: 118843
* Add support for Thumb2 encodings of NEON data processing instructions, using ↵Owen Anderson2010-11-111-0/+2
| | | | | | | | the new PostEncoderMethod infrastructure. More tests to come. llvm-svn: 118819
* Encoding of destination fixup for ARM branch and conditional branchJim Grosbach2010-11-111-0/+2
| | | | | | instructions. llvm-svn: 118801
* Encoding for ARM LDRSH_POST.Jim Grosbach2010-11-111-0/+2
| | | | llvm-svn: 118794
* ARM STRH encoding information.Jim Grosbach2010-11-111-0/+2
| | | | llvm-svn: 118757
* ARM LDM encoding for the mode (ia, ib, da, db) operand.Jim Grosbach2010-11-101-0/+2
| | | | llvm-svn: 118736
* Add encoder method for ARM load/store shifted register offset operands.Jim Grosbach2010-11-091-0/+2
| | | | llvm-svn: 118513
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-031-11/+30
| | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. llvm-svn: 118144
* Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to workBill Wendling2010-11-021-19/+20
| | | | | | | | with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. llvm-svn: 118094
* Rename encoder methods to match naming convention.Owen Anderson2010-11-021-5/+2
| | | | llvm-svn: 118093
* Add correct NEON encodings for vld2, vld3, and vld4 basic variants.Owen Anderson2010-11-021-0/+3
| | | | llvm-svn: 117997
* Add correct NEON encodings for the "multiple single elements" form of vld.Owen Anderson2010-11-021-1/+4
| | | | llvm-svn: 117984
* Encode the register list operands for ARM mode LDM/STM instructions.Jim Grosbach2010-10-301-0/+3
| | | | llvm-svn: 117753
* 80 column fix.Jim Grosbach2010-10-291-2/+2
| | | | llvm-svn: 117741
* s/getNEONVcvtImm32/getNEONVcvtImm32OpValue/ to be consistent with other operandJim Grosbach2010-10-291-1/+1
| | | | | | encoder functions. llvm-svn: 117738
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-2/+3
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
* Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson2010-10-271-0/+2
| | | | | | | | encoding for specifying fractional bits for fixed point conversions. llvm-svn: 117501
* JIT imm12 encoding for constant pool entry references.Jim Grosbach2010-10-271-0/+4
| | | | llvm-svn: 117483
* ARM JIT fix for LDRi12 and company.Jim Grosbach2010-10-271-4/+17
| | | | llvm-svn: 117478
* The new LDR* instruction patterns should handle the necessary encoding ofJim Grosbach2010-10-271-0/+7
| | | | | | | operands in the TableGen'erated bits, so we don't need to do the additional magic explicitly. llvm-svn: 117461
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-0/+2
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. llvm-svn: 117409
* fix memory-layout assumption which only holds on little-endian systemsGabor Greif2010-10-221-1/+1
| | | | llvm-svn: 117176
* ARM Binary encoding information for BFC/BFI instructions.Jim Grosbach2010-10-211-0/+2
| | | | llvm-svn: 117072
* Add encodings for movement between ARM core registers and single-precisionBill Wendling2010-10-201-1/+1
| | | | | | registers. llvm-svn: 116961
* ARMCodeEmitter::emitMiscInstruction is dead. Long liveBill Wendling2010-10-151-45/+1
| | | | | | ARMCodeEmitter::emitMiscInstruction! llvm-svn: 116644
* ARM mode encoding information for UBFX and SBFX instructions.Jim Grosbach2010-10-151-0/+2
| | | | llvm-svn: 116588
* Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'Jim Grosbach2010-10-141-2/+2
| | | | | | pseudonym. llvm-svn: 116512
* Add encoding for 'fmstat'.Bill Wendling2010-10-141-4/+0
| | | | llvm-svn: 116466
* - Add encodings for multiply add/subtract instructions in all their glory.Bill Wendling2010-10-141-9/+1
| | | | | | | - Add missing patterns for some multiply add/subtract instructions. - Add encodings for VMRS and VMSR. llvm-svn: 116464
* Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.Jim Grosbach2010-10-131-0/+2
| | | | llvm-svn: 116421
* Add the rest of the ARM so_reg encoding options (register shifted register)Jim Grosbach2010-10-121-0/+2
| | | | | | | and move to a custom operand encoder. Remove the last of the special handling stuff from ARMMCCodeEmitter::EncodeInstruction. llvm-svn: 116377
* Move the ARM so_imm encoding into a custom operand encoder and remove theJim Grosbach2010-10-121-0/+2
| | | | | | | explicit handling of the instructions referencing it from the MC code emitter. llvm-svn: 116367
* Add custom encoder for the 's' bit denoting whether an ARM arithmeticJim Grosbach2010-10-121-0/+11
| | | | | | | instruction should set the processor status flags or not. Remove the now unnecessary special handling for the bit from the MCCodeEmitter. llvm-svn: 116360
* Reapply 116059, this time without the fatfingered pasto at the top.Jim Grosbach2010-10-081-13/+17
| | | | | | ''const'ify getMachineOpValue() and associated helpers.' llvm-svn: 116067
* Reverting 116059. Bots are unhappy with it.Jim Grosbach2010-10-081-18/+14
| | | | llvm-svn: 116064
* 'const'ify getMachineOpValue() and associated helpers.Jim Grosbach2010-10-081-14/+18
| | | | llvm-svn: 116059
* Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.Jim Grosbach2010-10-081-1/+1
| | | | llvm-svn: 116018
* move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helperJim Grosbach2010-09-151-29/+22
| | | | | | | | | functions in ARMBaseInfo.h so it can be used in the MC library as well. For anything bigger than this, we may want a means to have a small support library for shared helper functions like this. Cross that bridge when we come to it. llvm-svn: 114016
* Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. CheckJim Grosbach2010-09-151-6/+6
| | | | | | if the register is a member of the SPR register class directly instead. llvm-svn: 114012
* zap dead code.Chris Lattner2010-09-041-4/+0
| | | | llvm-svn: 113073
* Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just likeBob Wilson2010-08-271-2/+2
| | | | | | | | | | | | | | | | | | | all the other LDM/STM instructions. This fixes asm printer crashes when compiling with -O0. I've changed one of the NEON tests (vst3.ll) to run with -O0 to check this in the future. Prior to this change VLDM/VSTM used addressing mode #5, but not really. The offset field was used to hold a count of the number of registers being loaded or stored, and the AM5 opcode field was expanded to specify the IA or DB mode, instead of the standard ADD/SUB specifier. Much of the backend was not aware of these special cases. The crashes occured when rewriting a frameindex caused the AM5 offset field to be changed so that it did not have a valid submode. I don't know exactly what changed to expose this now. Maybe we've never done much with -O0 and NEON. Regardless, there's no longer any reason to keep a count of the VLDM/VSTM registers, so we can use addressing mode #4 and clean things up in a lot of places. llvm-svn: 112322
* Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoidBob Wilson2010-08-171-0/+5
| | | | | | | printing "lsl #0". This fixes the remaining parts of pr7792. Make corresponding changes for encoding/decoding these instructions. llvm-svn: 111251
* Move the ARM SSAT and USAT optional shift amount operand out of theBob Wilson2010-08-111-5/+6
| | | | | | instruction opcode. This also fixes part of PR7792. llvm-svn: 110875
* Add a separate ARM instruction format for Saturate instructions.Bob Wilson2010-08-111-0/+45
| | | | | | | | | (I discovered 2 more copies of the ARM instruction format list, bringing the total to 4!! Two of them were already out of sync. I haven't yet gotten into the disassembler enough to know the best way to fix this, but something needs to be done.) Add support for encoding these instructions. llvm-svn: 110754
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110460
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | llvm-svn: 110410
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. llvm-svn: 110396
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