| Commit message (Collapse) | Author | Age | Files | Lines |
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expand the testing of the narrowing shift right instructions.
No functionality change.
llvm-svn: 127193
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Patch by Zonr Chang!
llvm-svn: 126967
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shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
llvm-svn: 126723
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(yes, this is different from R_ARM_CALL)
- Adds a new method getARMBranchTargetOpValue() which handles the
necessary distinction between the conditional and unconditional br/bl
needed for ARM/ELF
At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...
Added a few FIXME's for future naming fixups in ARMInstrInfo.td
llvm-svn: 124895
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instruction
llvm-svn: 123770
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in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.
llvm-svn: 123369
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llvm-svn: 121798
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instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.
The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.
There are some obvious cleanups here, which will happen shortly.
llvm-svn: 121747
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much later, which makes the entire
process cleaner.
llvm-svn: 121735
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llvm-svn: 121726
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Provide correct fixups for Thumb2 ADR,
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.
llvm-svn: 121721
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branch with a null predicate, or
as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.
llvm-svn: 121710
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llvm-svn: 121581
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llvm-svn: 121496
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llvm-svn: 121493
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t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>
llvm-svn: 121417
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llvm-svn: 121399
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particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.
Attempt to get the encoding at slightly more correct with this.
llvm-svn: 121336
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llvm-svn: 121308
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llvm-svn: 121226
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llvm-svn: 121186
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llvm-svn: 121072
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encoding if we're in that mode.
llvm-svn: 120608
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instruction at MC lowering. Add binary encoding information for the ADR,
including fixup data for the label operand.
llvm-svn: 120594
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Additionally, update these to unified syntax.
llvm-svn: 120589
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t_addrmode_s4, but with a different scaling factor.
* Encode the Thumb1 load and store instructions. This involved a bit of
refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
were removed.
llvm-svn: 120482
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llvm-svn: 120449
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certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
llvm-svn: 120408
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and which are pseudos.
llvm-svn: 120366
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llvm-svn: 120364
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The only reasonable way I could find to do this is to provide an alternate
version of the addrmode6 operand with a different encoding function. Use it
for all the VLD-dup instructions for the sake of consistency.
llvm-svn: 120358
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llvm-svn: 120340
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value that the one in ARMMCCodeEmitter.cpp does.
llvm-svn: 119878
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llvm-svn: 119767
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.o path now works for ARM.
Note: lo16AllZero remains in ARMInstrInfo.td - It can be factored out when Thumb movt is repaired.
Existing tests cover this update.
llvm-svn: 119760
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it as such. Add some encoding information.
llvm-svn: 119588
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llvm-svn: 119573
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should get the submode from the load/store multiple instruction's opcode.
llvm-svn: 119461
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llvm-svn: 119180
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movi+orr or movw+movt depending on the subtarget.
llvm-svn: 118938
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llvm-svn: 118924
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llvm-svn: 118854
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llvm-svn: 118843
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the new PostEncoderMethod infrastructure.
More tests to come.
llvm-svn: 118819
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instructions.
llvm-svn: 118801
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llvm-svn: 118794
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llvm-svn: 118757
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llvm-svn: 118736
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llvm-svn: 118513
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
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