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* Teach two-address pass to do some coalescing while eliminating REG_SEQUENCEEvan Cheng2010-05-141-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | instructions. e.g. %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1027<def> = EXTRACT_SUBREG %reg1026, 6 %reg1028<def> = EXTRACT_SUBREG %reg1026<kill>, 5 ... %reg1029<def> = REG_SEQUENCE %reg1028<kill>, 5, %reg1027<kill>, 6, %reg1028, 7, %reg1027, 8, %reg1028, 9, %reg1027, 10, %reg1030<kill>, 11, %reg1032<kill>, 12 After REG_SEQUENCE is eliminated, we are left with: %reg1026<def> = VLDMQ %reg1025<kill>, 260, pred:14, pred:%reg0 %reg1029:6<def> = EXTRACT_SUBREG %reg1026, 6 %reg1029:5<def> = EXTRACT_SUBREG %reg1026<kill>, 5 The regular coalescer will not be able to coalesce reg1026 and reg1029 because it doesn't know how to combine sub-register indices 5 and 6. Now 2-address pass will consult the target whether sub-registers 5 and 6 of reg1026 can be combined to into a larger sub-register (or combined to be reg1026 itself as is the case here). If it is possible, it will be able to replace references of reg1026 with reg1029 + the larger sub-register index. llvm-svn: 103835
* Change the Value argument to eliminateFrameIndex to a type-tagged value. ThisJim Grosbach2010-03-091-1/+1
| | | | | | | | | | is preparatory to having PEI's scavenged frame index value reuse logic properly distinguish types of frame values (e.g., whether the value is stack-pointer relative or frame-pointer relative). No functionality change. llvm-svn: 98086
* Updated version of r96634 (which was reverted due to failing 176.gcc andJim Grosbach2010-02-221-0/+1
| | | | | | | | 126.gcc nightly tests. These failures uncovered latent bugs that machine DCE could remove one half of a stack adjust down/up pair, causing PEI to assert. This update fixes that, and the tests now pass. llvm-svn: 96822
* Revert 96634. It causes assertion failures for 126.gcc and 176.gcc inBob Wilson2010-02-191-1/+0
| | | | | | the armv6 nightly tests. llvm-svn: 96691
* Radar 7636153. In the presence of large call frames, it's not sufficientJim Grosbach2010-02-191-0/+1
| | | | | | | | | for ARM to just check if a function has a FP to determine if it's safe to simplify the stack adjustment pseudo ops prior to eliminating frame indices. Allow targets to override the default behavior and does so for ARM and Thumb2. llvm-svn: 96634
* constify a method argument.Chris Lattner2010-01-261-2/+2
| | | | llvm-svn: 94612
* For aligned load/store instructions, it's only required to know whether aJim Grosbach2010-01-191-0/+1
| | | | | | | | | | | function can support dynamic stack realignment. That's a much easier question to answer at instruction selection stage than whether the function actually will have dynamic alignment prologue. This allows the removal of the stack alignment heuristic pass, and improves code quality for cases where the heuristic would result in dynamic alignment code being generated when it was not strictly necessary. llvm-svn: 93885
* Generate more correct debug info for frame indices.Jim Grosbach2009-11-221-0/+3
| | | | llvm-svn: 89576
* Make the MachineFunction argument of getFrameRegister const.David Greene2009-11-121-1/+1
| | | | | | This also fixes a build error. llvm-svn: 87027
* Infrastructure for dynamic stack realignment on ARM. For now, this is off byJim Grosbach2009-10-271-0/+2
| | | | | | | default behind a command line option. This will enable better performance for vectors on NEON enabled processors. llvm-svn: 85333
* Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.Evan Cheng2009-10-251-0/+7
| | | | llvm-svn: 85049
* Enable post-pass frame index register scavenging for ARM and Thumb2Jim Grosbach2009-10-201-0/+2
| | | | llvm-svn: 84585
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-2/+3
| | | | | | | | | | | | | | | | | | | | a virtual register to eliminate a frame index, it can return that register and the constant stored there to PEI to track. When scavenging to allocate for those registers, PEI then tracks the last-used register and value, and if it is still available and matches the value for the next index, reuses the existing value rather and removes the re-materialization instructions. Fancier tracking and adjustment of scavenger allocations to keep more values live for longer is possible, but not yet implemented and would likely be better done via a different, less special-purpose, approach to the problem. eliminateFrameIndex() is modified so the target implementations can return the registers they wish to be tracked for reuse. ARM Thumb1 implements and utilizes the new mechanism. All other targets are simply modified to adjust for the changed eliminateFrameIndex() prototype. llvm-svn: 83467
* Do not use frame register to reference fixed stack objects if the function ↵Evan Cheng2009-08-151-1/+1
| | | | | | is frameless. llvm-svn: 79067
* Leaf functions which do not save CSRs can be frameless even with ↵Evan Cheng2009-08-141-0/+2
| | | | | | -disable-fp-elim. llvm-svn: 79039
* When fp is not eliminated, instructions with T2_i12 modes will be changed to ↵Evan Cheng2009-07-301-0/+2
| | | | | | T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. llvm-svn: 77642
* Give getPointerRegClass() a "kind" value so that targets can Chris Lattner2009-07-291-2/+2
| | | | | | support multiple different pointer register classes. llvm-svn: 77501
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-18/+2
| | | | | | | | | | | - This change also makes it possible to switch between ARM / Thumb on a per-function basis. - Fixed thumb2 routine which expand reg + arbitrary immediate. It was using using ARM so_imm logic. - Use movw and movt to do reg + imm when profitable. - Other code clean ups and minor optimizations. llvm-svn: 77300
* Refactor. Get rid of a few more getOpcode() calls.Evan Cheng2009-07-261-4/+16
| | | | llvm-svn: 77164
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index ↵David Goodwin2009-07-241-7/+4
| | | | | | elimination more exactly for Thumb-2 to get better code gen. llvm-svn: 76919
* Fix frame index elimination to correctly handle thumb-2 addressing modes ↵David Goodwin2009-07-231-0/+7
| | | | | | that don't allow negative offsets. During frame elimination convert *i12 opcode to a *i8 when necessary due to a negative offset. llvm-svn: 76883
* Get rid one of the getRegisterNumbering. Also add D16 - D31.Evan Cheng2009-07-221-6/+4
| | | | llvm-svn: 76725
* Let callers decide the sub-register index on the def operand of ↵Evan Cheng2009-07-161-1/+2
| | | | | | | | rematerialized instructions. Avoid remat'ing instructions whose def have sub-register indices for now. It's just really really hard to get all the cases right. llvm-svn: 75900
* 80 col violation.Evan Cheng2009-07-101-1/+2
| | | | llvm-svn: 75212
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-1/+4
| | | | llvm-svn: 75036
* Push methods into base class in preparation for sharing.David Goodwin2009-07-081-6/+33
| | | | llvm-svn: 75020
* Start breaking out common base functionality for register info.David Goodwin2009-07-081-0/+113
llvm-svn: 75016
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