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authorEvan Cheng <evan.cheng@apple.com>2009-10-25 07:53:28 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-10-25 07:53:28 +0000
commit2e7dee5f23559a5c41c18635305c98bf443c4569 (patch)
tree36be38539a40407e1b4ce9ea7ca2c8bc746261db /llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
parent5d1b8496584341474c808848c9814f984b33be4b (diff)
downloadbcm5719-llvm-2e7dee5f23559a5c41c18635305c98bf443c4569.tar.gz
bcm5719-llvm-2e7dee5f23559a5c41c18635305c98bf443c4569.zip
Add ARM getMatchingSuperRegClass to handle S / D / Q cross regclass coalescing.
llvm-svn: 85049
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseRegisterInfo.h')
-rw-r--r--llvm/lib/Target/ARM/ARMBaseRegisterInfo.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
index f7d38e540de..750d29f8d6a 100644
--- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.h
@@ -74,6 +74,13 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const;
+ /// getMatchingSuperRegClass - Return a subclass of the specified register
+ /// class A so that each register in it has a sub-register of the
+ /// specified sub-register index which is in the specified register class B.
+ virtual const TargetRegisterClass *
+ getMatchingSuperRegClass(const TargetRegisterClass *A,
+ const TargetRegisterClass *B, unsigned Idx) const;
+
const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
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