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* [ARM] Use the efficient version of BitVector::set and a static_assert.Benjamin Kramer2016-01-141-3/+2
| | | | | | No functional change intended. llvm-svn: 257766
* CXX_FAST_TLS calling convention: performance improvement for ARM.Manman Ren2016-01-121-1/+12
| | | | | | | This is the same change on ARM as r255821 on AArch64. rdar://9001553 llvm-svn: 257424
* CXX_FAST_TLS calling convention: Add support for ARM on Darwin.Manman Ren2016-01-111-0/+4
| | | | | | rdar://9001553 llvm-svn: 257417
* ARM: support TLS accesses on Darwin platformsTim Northover2016-01-071-0/+8
| | | | | | | | Darwin TLS accesses most closely resemble ELF's general-dynamic situation, since they have to be able to handle all possible situations. The descriptors and so on are obviously slightly different though. llvm-svn: 257039
* Targets: commonize some stack realignment codeJF Bastien2015-07-201-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: * Fix FIXME on `needsStackRealignment`: it is now shared between multiple targets, implemented in `TargetRegisterInfo`, and isn't `virtual` anymore. This will break out-of-tree targets, silently if they used `virtual` and with a build error if they used `override`. * Factor out `canRealignStack` as a `virtual` function on `TargetRegisterInfo`, by default only looks for the `no-realign-stack` function attribute. Multiple targets duplicated the same `needsStackRealignment` code: - Aarch64. - ARM. - Mips almost: had extra `DEBUG` diagnostic, which the default implementation now has. - PowerPC. - WebAssembly. - x86 almost: has an extra `-force-align-stack` option, which the default implementation now has. The default implementation of `needsStackRealignment` used to just return `false`. My current patch changes the behavior by simply using the above shared behavior. This affects: - AMDGPU - BPF - CppBackend - MSP430 - NVPTX - Sparc - SystemZ - XCore - Out-of-tree targets This is a breaking change! `make check` passes. The only implementation of the `virtual` function (besides the slight different in x86) was Hexagon (which did `MF.getFrameInfo()->getMaxAlignment() > 8`), and potentially some out-of-tree targets. Hexagon now uses the default implementation. `needsStackRealignment` was being overwritten in `<Target>GenRegisterInfo.inc`, to return `false` as the default also did. That was odd and is now gone. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11160 llvm-svn: 242727
* TargetRegisterInfo: Provide a way to check assigned registers in ↵Matthias Braun2015-07-151-1/+2
| | | | | | | | | | getRegAllocationHints() Pass a const reference to LiveRegMatrix to getRegAllocationHints() because some targets can prodive better hints if they can test whether a physreg has been used for register allocation yet. llvm-svn: 242340
* Target RegisterInfo: devirtualize TargetFrameLoweringJF Bastien2015-07-101-10/+10
| | | | | | | | | | | | | Summary: The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can. This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here. Subscribers: sunfish, ted, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11093 llvm-svn: 241921
* ARM: Handle physreg targets in RegPair hints gracefullyMatthias Braun2015-04-031-6/+15
| | | | | | | | Register coalescing can change the target of a RegPair hint to a physreg, we should not crash on this. This also slightly improved the way ARMBaseRegisterInfo::updateRegAllocHint() works. llvm-svn: 233987
* [ARM] Fix handling of thumb1 out-of-range frame offsetsJohn Brawn2015-03-201-5/+4
| | | | | | | | | | | | | | | | LocalStackSlotPass assumes that isFrameOffsetLegal doesn't change its answer when the base register changes. Unfortunately this isn't true in thumb1, where SP-based loads allow a larger offset than non-SP-based loads, and this causes the base register reuse code to generate instructions that are unencodable, causing an assertion failure. Solve this by adding a BaseReg parameter to isFrameOffsetLegal, which ARMBaseRegisterInfo can then make use of to give the correct answer. Differential Revision: http://reviews.llvm.org/D8419 llvm-svn: 232825
* [ARM] Fix offset calculation in ARMBaseRegisterInfo::needsFrameBaseRegRichard Barton2015-03-171-1/+0
| | | | | | | | | | | | | The input offset to needsFrameBaseReg is a negative value below the top of the stack frame, but when converting to a positive offset from the bottom of the stack frame this value was negated, causing the final offset to be too large by twice the input offset's magnitude. Fix that by not negating the offset. Patch by John Brawn Differential Revision: http://reviews.llvm.org/D8316 llvm-svn: 232513
* Remove the need to cache the subtarget in the ARM TargetRegisterInfoEric Christopher2015-03-121-12/+20
| | | | | | | classes. Replace the frame pointer initialization with a static function that'll look it up via the subtarget on the MachineFunction. llvm-svn: 232010
* Have getCallPreservedMask and getThisCallPreservedMask take aEric Christopher2015-03-111-4/+6
| | | | | | | MachineFunction argument so that we can grab subtarget specific features off of it. llvm-svn: 231979
* Have getCalleeSavedRegs take a non-null MachineFunction all theEric Christopher2015-03-111-2/+0
| | | | | | | | time. The target independent code was passing in one all the time and targets weren't checking validity before using. Update a few calls to pass in a MachineFunction where necessary. llvm-svn: 231970
* Have TargetRegisterInfo::getLargestLegalSuperClass take aEric Christopher2015-03-101-3/+3
| | | | | | | MachineFunction argument so that it can look up the subtarget rather than using a cached one in some Targets. llvm-svn: 231888
* Remove dead code.Eric Christopher2015-03-101-23/+0
| | | | llvm-svn: 231883
* Improve handling of stack accesses in Thumb-1Renato Golin2015-02-251-3/+4
| | | | | | | | | | | | | | | | | Thumb-1 only allows SP-based LDR and STR to be word-sized, and SP-base LDR, STR, and ADD only allow offsets that are a multiple of 4. Make some changes to better make use of these instructions: * Use word loads for anyext byte and halfword loads from the stack. * Enforce 4-byte alignment on objects accessed in this way, to ensure that the offset is valid. * Do the same for objects whose frame index is used, in order to avoid having to use more than one ADD to generate the frame index. * Correct how many bits of offset we think AddrModeT1_s has. Patch by John Brawn. llvm-svn: 230496
* Rename UpdateRegAllocHint to match style guidelines.Eric Christopher2015-02-241-1/+1
| | | | llvm-svn: 230357
* ARM: Canonicalize access to function attributes, NFCDuncan P. N. Exon Smith2015-02-141-4/+2
| | | | | | | | | | | | Canonicalize access to function attributes to use the simpler API. getAttributes().getAttribute(AttributeSet::FunctionIndex, Kind) => getFnAttribute(Kind) getAttributes().hasAttribute(AttributeSet::FunctionIndex, Kind) => hasFnAttribute(Kind) llvm-svn: 229220
* Migrate ARM except for TTI, AsmPrinter, and frame loweringEric Christopher2015-01-291-8/+3
| | | | | | away from getSubtargetImpl. llvm-svn: 227399
* ARM: convert isTargetIOS checks to isTargetDarwin.Tim Northover2014-12-111-7/+5
| | | | | | | | | | | The distinction is mostly useful in the front-end. By the time we get here, there are very few situations where we actually want different behaviour for Darwin and IOS (in fact Darwin mostly just exists in a few tests). So this should reduce any surprising weirdness for anyone using it. No functional change on anything anyone actually cares about. llvm-svn: 224035
* ARM: rework Thumb1 frame index rewritingTim Northover2014-10-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | The previous code had a few problems, motivating the choices here. 1. It could create instructions clobbering CPSR, but the incoming MachineInstr didn't reflect this. A potential source of corruption. This is why the patch has a new PseudoInst for before lowering. 2. Similarly, there was some code to handle the incoming instruction not being ARMCC::AL, but this would have caused massive problems if it was actually invoked when a complex offset needing more than one instruction was requested. 3. It wasn't designed to handle unaligned pointers (or offsets). These should probably be minimised anyway, but the code needs to deal with them properly regardless. 4. It had some rather dubious ad-hoc code to avoid calling emitThumbRegPlusImmediate, a function which should be designed to do precisely this job. We seem to cover the common cases correctly now, and hopefully can enhance emitThumbRegPlusImmediate to handle any extra optimisations we need to add in future. llvm-svn: 220236
* Revert 202433 - Provide a target override for the latest regalloc heuristicRenato Golin2014-10-031-5/+0
| | | | | | | | | | | That commit was introduced in order to help investigate a problem in ARM codegen breaking from commit 202304 (Add a limit to the heuristic that register allocates instructions in local order). Recent analisys indicated that the problem no longer exists, so I'm reverting this change. See PR18996. llvm-svn: 218981
* ARM: allow copying of CPSR when all else fails.Tim Northover2014-10-011-1/+1
| | | | | | | | | | | | As with x86 and AArch64, certain situations can arise where we need to spill CPSR in the middle of a calculation. These should be avoided where possible (MRS/MSR is rather expensive), which ARM is actually better at than the other two since it tries to Glue defs to uses, but as a last ditch effort, copying is better than crashing. rdar://problem/18011155 llvm-svn: 218789
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-19/+10
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-13/+28
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* [RegisterCoalescer] Moving the RegisterCoalescer subtarget hook onto the ↵Chris Bieneman2014-07-161-0/+59
| | | | | | TargetRegisterInfo instead of the TargetSubtargetInfo. llvm-svn: 213188
* ARM: use AAPCS-style prologues for embedded MachO.Tim Northover2014-05-301-3/+6
| | | | | | | | | | | | | | | Darwin prologues save their GPRs in two stages: a narrow push of r0-r7 & lr, followed by a wide push of the remaining registers if there are any. AAPCS uses a single push.w instruction. It turns out that, on average, enough registers get pushed that code is smaller in the AAPCS prologue, which is a nice property for M-class programmers. They also have other options available for back-traces, so can hopefully deal with the fact that FP & LR aren't adjacent in memory. rdar://problem/15909583 llvm-svn: 209895
* ARM: improve WoA ABI conformance for frame registerSaleem Abdulrasool2014-05-181-3/+7
| | | | | | | | | Windows on ARM uses R11 for the frame pointer even though the environment is a pure Thumb-2, thumb-only environment. Replicate this behaviour to improve Windows ABI compatibility. This register is used for fast stack walking, and thus is part of the Windows ABI. llvm-svn: 209085
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-041-2/+2
| | | | llvm-svn: 205610
* Simplify resolveFrameIndex() signature.Jim Grosbach2014-04-021-4/+2
| | | | | | | | Just pass a MachineInstr reference rather than an MBB iterator. Creating a MachineInstr& is the first thing every implementation did anyway. llvm-svn: 205453
* Provide a target override for the latest regalloc heuristic.Andrew Trick2014-02-271-0/+5
| | | | | | | This is a temporary workaround for native arm linux builds: PR18996: Changing regalloc order breaks "lencod" on native arm linux builds. llvm-svn: 202433
* Revert r200095 and r200152. It turns out when compiling with -arch armv7 ↵Evan Cheng2014-02-061-3/+4
| | | | | | -mcpu=cortex-m3, the triple would still set iOS as the OS so the hack is still needed. rdar://15984891 llvm-svn: 200937
* Follow up of r200095. Code clean up.Evan Cheng2014-01-261-1/+1
| | | | llvm-svn: 200152
* Clean up hack which is no longer needed after r198617. No functionality change.Evan Cheng2014-01-251-3/+2
| | | | llvm-svn: 200095
* ARM MachO: sort out isTargetDarwin/isTargetIOS/... checks.Tim Northover2014-01-061-1/+1
| | | | | | | | | | | | | | | | | | The ARM backend has been using most of the MachO related subtarget checks almost interchangeably, and since the only target it's had to run on has been IOS (which is all three of MachO, Darwin and IOS) it's worked out OK so far. But we'd like to support embedded targets under the "*-*-none-macho" triple, which means everything starts falling apart and inconsistent behaviours emerge. This patch should pick a reasonably sensible set of behaviours for the new triple (and any others that come along, with luck). Some choices were debatable (notably FP == r7 or r11), but we can revisit those later when deficiencies become apparent. llvm-svn: 198617
* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-071-8/+0
| | | | | | They haven't been used for a long time. Patch by MathOnNapkins. llvm-svn: 192099
* ARM: support interrupt attributeTim Northover2013-10-011-11/+25
| | | | | | | | | | | This function-attribute modifies the callee-saved register list and function epilogue (specifically the return instruction) so that a routine is suitable for use as an interrupt-handler of the specified type without disrupting user-mode applications. rdar://problem/14207019 llvm-svn: 191766
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-011-1/+1
| | | | | | | | Function attributes are the future! So just query whether we want to realign the stack directly from the function instead of through a random target options structure. llvm-svn: 187618
* Have ARMBaseRegisterInfo::getCallPreservedMask return the 'correct' mask for ↵Stephen Lin2013-07-031-4/+13
| | | | | | | | the GHC calling convention. This is purely academic because GHC calls are always tail calls so the register mask will never be used; however, this change makes the code clearer and brings the ARM implementation of the GHC calling convention in line with the X86 implementation. Also, it might save someone else some time trying to figuring out what is happening... llvm-svn: 185592
* Clarify and doxygen-ify commentsStephen Lin2013-06-261-8/+12
| | | | llvm-svn: 185030
* ARM: Proactively ensure that the LowerCallResult hack for 'this'-returns is ↵Stephen Lin2013-06-261-0/+3
| | | | | | | | not used for incompatible calling conventions. (Currently, ARM 'this'-returns are handled in the standard calling convention case by treating R0 as preserved and doing some extra magic in LowerCallResult; this may not apply to calling conventions added in the future so this patch provides and documents an interface for indicating such) llvm-svn: 185024
* Minor formatting fix to ARMBaseRegisterInfo::getCalleeSavedRegsStephen Lin2013-06-261-7/+5
| | | | llvm-svn: 185016
* Debug Info: Simplify Frame Index handling in DBG_VALUE Machine InstructionsDavid Blaikie2013-06-161-6/+1
| | | | | | | | | | | | | | | | | | | | Rather than using the full power of target-specific addressing modes in DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This reduces the complexity of debug info handling down to two representations of values (reg+offset and frame index+offset) rather than three or four. Ideally we could ensure that frame indicies had been eliminated by the time we reached an assembly or dwarf generation, but I haven't spent the time to figure out where the FIs are leaking through into that & whether there's a good place to convert them. Some FI+offset=>reg+offset conversion is done (see PrologEpilogInserter, for example) which is necessary for some SelectionDAG assumptions about registers, I believe, but it might be possible to make this a more thorough conversion & ensure there are no remaining FIs no matter how instruction selection is performed. llvm-svn: 184066
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-5/+10
| | | | | | the internals of TargetMachine could change. llvm-svn: 183488
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa2013-05-131-0/+1
| | | | | | instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
* Add CodeGen support for functions that always return arguments via a new ↵Stephen Lin2013-04-201-0/+6
| | | | | | parameter attribute 'returned', which is taken advantage of in target-independent tail call opportunity detection and in ARM call lowering (when placed on an integral first parameter). llvm-svn: 179925
* Allow the register scavenger to spill multiple registersHal Finkel2013-03-221-1/+1
| | | | | | | | | | | | | | | | | | This patch lets the register scavenger make use of multiple spill slots in order to guarantee that it will be able to provide multiple registers simultaneously. To support this, the RS's API has changed slightly: setScavengingFrameIndex / getScavengingFrameIndex have been replaced by addScavengingFrameIndex / isScavengingFrameIndex / getScavengingFrameIndices. In forthcoming commits, the PowerPC backend will use this capability in order to implement the spilling of condition registers, and some special-purpose registers, without relying on r0 being reserved. In some cases, spilling these registers requires two GPRs: one for addressing and one to hold the value being transferred. llvm-svn: 177774
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-211-58/+0
| | | | | | | | | | | | | | | to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. llvm-svn: 175788
* ARM: Allocation hints must make sure to be in the alloc order.Jim Grosbach2013-02-191-1/+2
| | | | | | | | | When creating an allocation hint for a register pair, make sure the hint for the physical register reference is still in the allocation order. rdar://13240556 llvm-svn: 175541
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