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* Remove extra semi-colons.Chad Rosier2012-02-221-1/+1
| | | | llvm-svn: 151169
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* Re-enable 150652 and 150654 - Make FPSCR non-reserved, and make MachineCSE ↵Lang Hames2012-02-171-1/+0
| | | | | | bail on reserved registers. This *should* be safe as of r150786. llvm-svn: 150769
* Oop - r150653 + r150654 broke one of my test cases. Backing out for now...Lang Hames2012-02-161-0/+1
| | | | llvm-svn: 150655
* FPSCR shouldn't be reserved.Lang Hames2012-02-161-1/+0
| | | | llvm-svn: 150654
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-4/+0
| | | | llvm-svn: 148578
* Implement ARMBaseRegisterInfo::getCallPreservedMask().Jakob Stoklund Olesen2012-01-171-19/+5
| | | | | | Move ARM callee-saved lists into ARMCallingConv.td. llvm-svn: 148357
* Reapply r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-051-1/+1
| | | | | | | | | | | | Now that canRealignStack() understands frozen reserved registers, it is safe to use it for aligned spill instructions. It will only return true if the registers reserved at the beginning of register allocation allow for dynamic stack realignment. <rdar://problem/10625436> llvm-svn: 147579
* Avoid reserving an ARM base pointer during register allocation.Jakob Stoklund Olesen2012-01-051-2/+17
| | | | | | | | | | | | | | | | | Once register allocation has started the reserved registers are frozen. Fix the ARM canRealignStack() hook to respect the frozen register state. Now the hook returns false if register allocation was started with frame pointer elimination enabled. It also returns false if register allocation started without a reserved base pointer, and stack realignment would require a base pointer. This bug was breaking oggenc on armv6. No test case, an upcoming patch will use this functionality to realign the stack for spill slots when possible. llvm-svn: 147578
* Revert r146997, "Heed spill slot alignment on ARM."Jakob Stoklund Olesen2012-01-031-1/+1
| | | | | | | | | This patch caused a miscompilation of oggenc because a frame pointer was suddenly needed halfway through register allocation. <rdar://problem/10625436> llvm-svn: 147487
* Heed spill slot alignment on ARM.Jakob Stoklund Olesen2011-12-201-1/+1
| | | | | | | | | | | Use the spill slot alignment as well as the local variable alignment to determine when the stack needs to be realigned. This works now that the ARM target can always realign the stack by using a base pointer. Still respect the ARMBaseRegisterInfo::canRealignStack() function vetoing a realigned stack. Don't use aligned spill code in that case. llvm-svn: 146997
* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-201-3/+3
| | | | llvm-svn: 146981
* Emit a getMatchingSuperRegClass() implementation for every target.Jakob Stoklund Olesen2011-12-191-98/+0
| | | | | | | | | Use information computed while inferring new register classes to emit accurate, table-driven implementations of getMatchingSuperRegClass(). Delete the old manual, error-prone implementations in the targets. llvm-svn: 146873
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-2/+2
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(Chad Rosier2011-10-201-2/+5
| | | | llvm-svn: 142557
* Add support for dynamic stack realignment when in thumb1 mode.Chad Rosier2011-10-181-5/+2
| | | | | | rdar://10288916 llvm-svn: 142337
* Revert r141529. This is causing failures in the test-suite, like bigstack ↵Bill Wendling2011-10-111-11/+2
| | | | | | and ReedSolomon. Boo... llvm-svn: 141716
* When getting the number of bits necessary for addressing modeBill Wendling2011-10-101-2/+11
| | | | | | | | ARMII::AddrModeT1_s, we need to take into account that if the frame register is ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of bits is 5. llvm-svn: 141529
* Revert r140924 "Attempt to fix dynamic stack realignment for thumb1 functions."Chad Rosier2011-10-011-2/+5
| | | | | | to appease nightly testers. Not quite there yet. llvm-svn: 140953
* Attempt to fix dynamic stack realignment for thumb1 functions. It is in fact Chad Rosier2011-10-011-5/+2
| | | | | | | | useful if an optimization assumes the stack has been realigned. Credit to Eli for his assistance. rdar://10043857 llvm-svn: 140924
* Store sub-class lists as a bit vector.Jakob Stoklund Olesen2011-09-301-1/+1
| | | | | | | | | | | | | | This uses less memory and it reduces the complexity of sub-class operations: - hasSubClassEq() and friends become O(1) instead of O(N). - getCommonSubClass() becomes O(N) instead of O(N^2). In the future, TableGen will infer register classes. This makes it cheap to add them. llvm-svn: 140898
* Tidy up a bit.Jim Grosbach2011-09-131-152/+78
| | | | llvm-svn: 139635
* Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng2011-08-301-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-241-3/+3
| | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. llvm-svn: 138445
* Silence a bunch (but not all) "variable written but not read" warningsDuncan Sands2011-08-121-0/+1
| | | | | | when building with assertions disabled. llvm-svn: 137460
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. llvm-svn: 135636
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-181-1/+0
| | | | | | better location welcome). llvm-svn: 135438
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-13/+1
| | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. llvm-svn: 135424
* Migrate LLVM and Clang to use the new makeArrayRef(...) functions where ↵Frits van Bommel2011-07-181-12/+12
| | | | | | | | previously explicit non-default constructors were used. Mostly mechanical with some manual reformatting. llvm-svn: 135390
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-1/+0
| | | | | | registeration and creation code into XXXMCDesc libraries. llvm-svn: 135184
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-291-4/+0
| | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. llvm-svn: 134114
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-2/+1
| | | | llvm-svn: 134030
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-281-2/+1
| | | | llvm-svn: 134027
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-5/+5
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-271-1/+1
| | | | llvm-svn: 133944
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-271-1/+3
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-241-3/+4
| | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. llvm-svn: 133782
* Reserve D16-D13 on subtargets that don't support them.Jakob Stoklund Olesen2011-06-181-0/+6
| | | | llvm-svn: 133321
* Explicitly invoke ArrayRef constructor to keep gcc happy.Jakob Stoklund Olesen2011-06-171-12/+12
| | | | | | Patch by Richard Smith! llvm-svn: 133220
* Rename TRI::getAllocationOrder() to getRawAllocationOrder().Jakob Stoklund Olesen2011-06-161-38/+22
| | | | | | | | | | | Also switch the return type to ArrayRef<unsigned> which works out nicely for ARM's implementation of this function because of the clever ArrayRef constructors. The name change indicates that the returned allocation order may contain reserved registers as has been the case for a while. llvm-svn: 133216
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-301-0/+4
| | | | | | | | directives. Fixes PR9826. llvm-svn: 132317
* Reuse the TargetInstrDesc.Cameron Zwarich2011-05-191-2/+1
| | | | llvm-svn: 131625
* Correctly constrain a register class when computing frame offsets, as the Thumb2Cameron Zwarich2011-05-191-0/+4
| | | | | | add instruction takes an rGPR. This fixes the last of PR8825. llvm-svn: 131619
* Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on ↵Jakob Stoklund Olesen2011-04-261-0/+19
| | | | | | | | | | | | register class inflation. The hook will be used by the register allocator when recomputing register classes after removing constraints. Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure that the spill size doesn't change. llvm-svn: 130228
* Avoid write-after-write issue hazards for Cortex-A9.Bob Wilson2011-04-191-0/+23
| | | | | | | | | | | Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. llvm-svn: 129772
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* Ignore special ARM allocation hints for unexpected register classes.Jakob Stoklund Olesen2011-03-251-0/+4
| | | | | | | | | Add an assertion to linear scan to prevent it from allocating registers outside the register class. <rdar://problem/9183021> llvm-svn: 128254
* Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.Cameron Zwarich2011-03-071-0/+20
| | | | llvm-svn: 127175
* Implement frame unwinding information emission for Thumb1. Not finished yet ↵Anton Korobeynikov2011-03-051-2/+3
| | | | | | because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. llvm-svn: 127104
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-13/+13
| | | | | | and fixes here and there. llvm-svn: 123170
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