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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-25 01:48:18 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-03-25 01:48:18 +0000 |
| commit | a1e3156ebdcd2a65b90d2e4f8c73109c1cefaaae (patch) | |
| tree | 86bb5d9824b18025389a9b7271073e34c2b7244e /llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | |
| parent | d46932118612ec022248d05390d8e69283c56012 (diff) | |
| download | bcm5719-llvm-a1e3156ebdcd2a65b90d2e4f8c73109c1cefaaae.tar.gz bcm5719-llvm-a1e3156ebdcd2a65b90d2e4f8c73109c1cefaaae.zip | |
Ignore special ARM allocation hints for unexpected register classes.
Add an assertion to linear scan to prevent it from allocating registers outside
the register class.
<rdar://problem/9183021>
llvm-svn: 128254
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp index 9d7be660109..1918fd95852 100644 --- a/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp @@ -448,6 +448,10 @@ ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8 }; + // We only support even/odd hints for GPR and rGPR. + if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass) + return std::make_pair(RC->allocation_order_begin(MF), + RC->allocation_order_end(MF)); if (HintType == ARMRI::RegPairEven) { if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0) |
