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* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-30/+31
| | | | llvm-svn: 207197
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-221-3/+3
| | | | | | | | | | | | system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... llvm-svn: 206838
* [Modules] Make Support/Debug.h modular. This requires it to not changeChandler Carruth2014-04-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | behavior based on other files defining DEBUG_TYPE, which means it cannot define DEBUG_TYPE at all. This is actually better IMO as it forces folks to define relevant DEBUG_TYPEs for their files. However, it requires all files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't already. I've updated all such files in LLVM and will do the same for other upstream projects. This still leaves one important change in how LLVM uses the DEBUG_TYPE macro going forward: we need to only define the macro *after* header files have been #include-ed. Previously, this wasn't possible because Debug.h required the macro to be pre-defined. This commit removes that. By defining DEBUG_TYPE after the includes two things are fixed: - Header files that need to provide a DEBUG_TYPE for some inline code can do so by defining the macro before their inline code and undef-ing it afterward so the macro does not escape. - We no longer have rampant ODR violations due to including headers with different DEBUG_TYPE definitions. This may be mostly an academic violation today, but with modules these types of violations are easy to check for and potentially very relevant. Where necessary to suppor headers with DEBUG_TYPE, I have moved the definitions below the includes in this commit. I plan to move the rest of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big enough. The comments in Debug.h, which were hilariously out of date already, have been updated to reflect the recommended practice going forward. llvm-svn: 206822
* Spell the specialization namespace correctly.Benjamin Kramer2014-04-121-1/+3
| | | | | | Not sure why clang didn't diagnose this (GCC does). llvm-svn: 206117
* Make helper static and place random global into the llvm namespace.Benjamin Kramer2014-04-121-1/+1
| | | | llvm-svn: 206116
* ARM: teach LLVM that Cortex-A7 is very similar to A8.Tim Northover2014-04-011-7/+8
| | | | llvm-svn: 205314
* Fix PR19136: [ARM] Fix Folding SP Update into vpush/vpopWeiming Zhao2014-03-201-3/+13
| | | | | | | | | | | Sicne MBB->computeRegisterLivenes() returns Dead for sub regs like s0, d0 is used in vpop instead of updating sp, which causes s0 dead before its use. This patch checks the liveness of each subreg to make sure the reg is actually dead. llvm-svn: 204411
* Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changingOwen Anderson2014-03-131-2/+3
| | | | | | | | | | operator* on the by-operand iterators to return a MachineOperand& rather than a MachineInstr&. At this point they almost behave like normal iterators! Again, this requires making some existing loops more verbose, but should pave the way for the big range-based for-loop cleanups in the future. llvm-svn: 203865
* Replace PROLOG_LABEL with a new CFI_INSTRUCTION.Rafael Espindola2014-03-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The old system was fairly convoluted: * A temporary label was created. * A single PROLOG_LABEL was created with it. * A few MCCFIInstructions were created with the same label. The semantics were that the cfi instructions were mapped to the PROLOG_LABEL via the temporary label. The output position was that of the PROLOG_LABEL. The temporary label itself was used only for doing the mapping. The new CFI_INSTRUCTION has a 1:1 mapping to MCCFIInstructions and points to one by holding an index into the CFI instructions of this function. I did consider removing MMI.getFrameInstructions completelly and having CFI_INSTRUCTION own a MCCFIInstruction, but MCCFIInstructions have non trivial constructors and destructors and are somewhat big, so the this setup is probably better. The net result is that we don't create temporary labels that are never used. llvm-svn: 203204
* Simplify. No functionality change.Rafael Espindola2014-03-071-10/+2
| | | | llvm-svn: 203199
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-4/+3
| | | | | | Remove the old functions. llvm-svn: 202636
* ARMv8 IfConversion must skip narrow instructions that a) define CPSR and b) ↵Artyom Skrobov2014-02-261-0/+14
| | | | | | wouldn't affect CPSR in an IT block llvm-svn: 202257
* Test commitOliver Stannard2014-01-291-0/+1
| | | | llvm-svn: 200401
* For ARM, fix assertuib failures for some ld/st 3/4 instruction with wirteback.Jiangning Liu2014-01-161-0/+2
| | | | llvm-svn: 199369
* ARM AnalyzeBranch should ignore DEBUG_VALUES while analyzing terminators.Lang Hames2013-12-201-1/+1
| | | | | | Found by inspection by Julien Lerouge. Thanks Julian! llvm-svn: 197833
* Bug 18149: [AArch32] VSel instructions has no ARMCC fieldWeiming Zhao2013-12-061-7/+34
| | | | | | | | | The current peephole optimizing for compare inst assumes an instr that uses CPSR has an MO for ARM Cond code.However, for VSEL instructions (vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do they support the modification of Cond Code. llvm-svn: 196588
* ARM: decide whether to use movw/movt based on "minsize" attribute.Tim Northover2013-12-021-3/+3
| | | | llvm-svn: 196102
* ARM: add pseudo-instructions for lit-pool global materialisationTim Northover2013-12-021-1/+7
| | | | | | | | | | | | These are used by MachO only at the moment, and (much like the existing MOVW/MOVT set) work around the fact that the labels used in the actual instructions often contain PC-dependent components, which means that repeatedly materialising the same global can't be CSEed. With small modifications, it could be adapted to how ELF finds the address of _GLOBAL_OFFSET_TABLE_, which would give similar benefits in PIC mode there. llvm-svn: 196090
* ARM: fix bug in -Oz stack adjustment foldingTim Northover2013-12-011-7/+18
| | | | | | | | | | | Previously, we clobbered callee-saved registers when folding an "add sp, #N" into a "pop {rD, ...}" instruction. This change checks whether a register we're going to add to the "pop" could actually be live outside the function before doing so and should fix the issue. This should fix PR18081. llvm-svn: 196046
* ARM: remove special cases for Darwin dynamic-no-pic mode.Tim Northover2013-11-251-5/+1
| | | | | | | | | These are handled almost identically to static mode (and ELF's global address materialisation), except that a symbol may have "$non_lazy_ptr" appended. This can be handled by passing appropriate flags along with the instruction instead of using entirely separate pseudo-instructions. llvm-svn: 195655
* Fix a typo where we were creating <def,kill> operands instead ofLang Hames2013-11-221-1/+2
| | | | | | | | | | <def,dead> ones. Add an assertion to make sure we catch this in the future. Fixes <rdar://problem/15464559>. llvm-svn: 195401
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-1/+1
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-1/+1
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-1/+1
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* Enable generating legacy IT block for AArch32Weiming Zhao2013-11-131-1/+1
| | | | | | | | | | | | | | By default, the behavior of IT block generation will be determinated dynamically base on the arch (armv8 vs armv7). This patch adds backend options: -arm-restrict-it and -arm-no-restrict-it. The former one restricts the generation of IT blocks (the same behavior as thumbv8) for both arches. The later one allows the generation of legacy IT block (the same behavior as ARMv7 Thumb2) for both arches. Clang will support -mrestrict-it and -mno-restrict-it, which is compatible with GCC. llvm-svn: 194592
* ARM: fold prologue/epilogue sp updates into push/pop for code sizeTim Northover2013-11-081-0/+97
| | | | | | | | | | | | | | | | | | ARM prologues usually look like: push {r7, lr} sub sp, sp, #4 If code size is extremely important, this can be optimised to the single instruction: push {r6, r7, lr} where we don't actually care about the contents of r6, but pushing it subtracts 4 from sp as a side effect. This should implement such a conversion, predicated on the "minsize" function attribute (-Oz) since I've yet to find any code it actually makes faster. llvm-svn: 194264
* ARM: remove unnecessary state-tracking during frame lowering.Tim Northover2013-11-041-0/+8
| | | | | | | | | | | | | | | | | | | | | ResolveFrameIndex had what appeared to be a very nasty hack for when the frame-index referred to a callee-saved register. In this case it "adjusted" the offset so that the address was correct if (and only if) the MachineInstr immediately followed the respective push. This "worked" for all forms of GPR & DPR but was only ever used to set the frame pointer itself, and once this was put in a more sensible location the entire state-tracking machinery it relied on became redundant. So I stripped it. The only wrinkle is that "add r7, sp, #0" might theoretically be slower (need an actual ALU slot) compared to "mov r7, sp" so I added a micro-optimisation that also makes emitARMRegUpdate and emitT2RegUpdate also work when NumBytes == 0. No test changes since there shouldn't be any functionality change. llvm-svn: 194025
* ARM: Thumb2 copy for GPRPair needs to use thumb instructions.Jim Grosbach2013-10-221-1/+1
| | | | | | | | Use tMOVr instead of plain MOVr. rdar://15193017 llvm-svn: 193139
* ARM: Clean up copyPhysReg() a bit.Jim Grosbach2013-10-221-27/+47
| | | | | | No functional change, just cleaning things up for readability. llvm-svn: 193138
* ARM: optimizeSelect has to consider the previous register classMatthias Braun2013-10-041-4/+9
| | | | | | | | optimizeSelect folds (predicated) copy instructions, it must not ignore the original register class of the operand when replacing the register with the copies dest register. llvm-svn: 191963
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-031-69/+2
| | | | | | Patch by Artyom Skrobov. llvm-svn: 191885
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 llvm-svn: 191671
* Fix spelling.Robert Wilhelm2013-09-141-1/+1
| | | | llvm-svn: 190749
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-091-4/+78
| | | | | | | | | IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! llvm-svn: 190309
* Let t2LDRBi8 and t2LDRBi12 have same Base PointerRenato Golin2013-08-141-1/+14
| | | | | | | | | | | | | | When determining if two different loads are from the same base address, this patch allows one load to use a t2LDRi8 address mode and another to use a t2LDRi12 address mode. The current implementation is very conservative and this allows the case of differing Thumb2 byte loads to be considered. Allowing these differing modes instead of forcing the exact same opcode is useful for situations where one opcodes loads from a base address+1 and a second opcode loads for a base address-1. Patch by Daniel Stewart. llvm-svn: 188385
* Refactor AnalyzeBranch on ARM. The previous version did not always analyzeLang Hames2013-07-191-88/+67
| | | | | | | | | | | | | | | | | | indirect branches correctly. Under some circumstances, this led to the deletion of basic blocks that were the destination of indirect branches. In that case it left indirect branches to nowhere in the code. This patch replaces, and is more general than either of the previous fixes for indirect-branch-analysis issues, r181161 and r186461. For other branches (not indirect) this refactor should have *almost* identical behavior to the previous version. There are some corner cases where this refactor is able to analyze blocks that the previous version could not (e.g. this necessitated the update to thumb2-ifcvt2.ll). <rdar://problem/14464830> llvm-svn: 186735
* Related to r181161 - Indirect branches may not be the last branch in a basicLang Hames2013-07-161-0/+7
| | | | | | | | | | | | block. Blocks that have an indirect branch terminator, even if it's not the last terminator, should still be treated as unanalyzable. <rdar://problem/14437274> Reducing a useful regression test case is proving difficult - I hope to have one soon. llvm-svn: 186461
* Fix ARM paired GPR COPY loweringJF Bastien2013-07-121-0/+3
| | | | | | | | | | | | | ARM paired GPR COPY was being lowered to two MOVr without CC. This patch puts the CC back. My test is a reduction of the case where I encountered the issue, 64-bit atomics use paired GPRs. The issue only occurs with selectionDAG, FastISel doesn't encounter it so I didn't bother calling it. llvm-svn: 186226
* DebugInfo: remove target-specific Frame Index handling for DBG_VALUE ↵David Blaikie2013-06-161-10/+0
| | | | | | | | | | MachineInstrs Frame index handling is now target-agnostic, so delete the target hooks for creation & asm printing of target-specific addressing in DBG_VALUEs and any related functions. llvm-svn: 184067
* Machine Model: Add MicroOpBufferSize and resource BufferSize.Andrew Trick2013-06-151-2/+1
| | | | | | | | | | | | | Replace the ill-defined MinLatency and ILPWindow properties with with straightforward buffer sizes: MCSchedMode::MicroOpBufferSize MCProcResourceDesc::BufferSize These can be used to more precisely model instruction execution if desired. Disabled some misched tests temporarily. They'll be reenabled in a few commits. llvm-svn: 184032
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-2/+1
| | | | | | the internals of TargetMachine could change. llvm-svn: 183488
* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-051-0/+2
| | | | | | | | An instruction with less than 3 inputs is trivially a fast immediate shift. Reapply of 183256, should not have caused the tablegen segfault on linux either. llvm-svn: 183314
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-041-2/+0
| | | | llvm-svn: 183273
* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-041-0/+2
| | | | | | An instruction with less than 3 inputs is trivially a fast immediate shift. llvm-svn: 183256
* ARM AnalyzeBranch should conservatively return true when it sees a predicatedEvan Cheng2013-05-051-3/+9
| | | | | | | | | | indirect branch at the end of the BB. Otherwise if-converter, branch folding pass may incorrectly update its successor info if it consider BB as fallthrough to the next BB. rdar://13782395 llvm-svn: 181161
* ARM: Use ldrd/strd to spill 64-bit pairs when available.Tim Northover2013-04-211-17/+38
| | | | | | | This allows common sp-offsets to be part of the instruction and is probably faster on modern CPUs too. llvm-svn: 179977
* ARM: don't add FrameIndex offset for LDMIA (has no immediate)Tim Northover2013-04-201-1/+1
| | | | | | | | | | | | Previously, when spilling 64-bit paired registers, an LDMIA with both a FrameIndex and an offset was produced. This kind of instruction shouldn't exist, and the extra operand was being confused with the predicate, causing aborts later on. This removes the invalid 0-offset from the instruction being produced. llvm-svn: 179956
* ARM scheduler model: Swift has varying latencies, uops for simple ALU opsArnold Schwaighofer2013-04-051-0/+12
| | | | llvm-svn: 178842
* Enabling the generation of dependency breakers for partial updates on ↵Silviu Baranga2013-03-271-7/+5
| | | | | | Cortex-A15. Also fixing a small bug in getting the update clearence for VLD1LNd32. llvm-svn: 178134
* Adding an A15 specific optimization pass for interactions between S/D/Q ↵Silviu Baranga2013-03-151-1/+1
| | | | | | registers. The pass handles all the required transformations pre-regalloc. llvm-svn: 177169
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