summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
Commit message (Expand)AuthorAgeFilesLines
* Change TII isCopyInstr way of returning arguments(NFC)Petar Jovanovic2018-06-061-4/+5
* [NEON] Support VLD1xN intrinsics in AArch32 mode (LLVM part)Ivan A. Kosarev2018-06-021-0/+28
* Revert r333819 "[NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)"Ivan A. Kosarev2018-06-021-28/+0
* [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)Ivan A. Kosarev2018-06-021-0/+28
* [X86][MIPS][ARM] New machine instruction property 'isMoveReg'Petar Jovanovic2018-05-231-0/+18
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-2/+2
* [DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen2018-05-091-4/+4
* Remove \brief commands from doxygen comments.Adrian Prantl2018-05-011-1/+1
* [ARM] Change std::sort to llvm::sort in response to r327219Mandeep Singh Grang2018-04-051-6/+6
* [ARM] Fix codegen for VLD3/VLD4/VST3/VST4 with WBFlorian Hahn2018-03-021-0/+2
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-4/+0
* [ARM] f16 stack spill/reloadsSjoerd Meijer2018-02-141-1/+21
* [ARM] Armv8.2-A FP16 code generation (part 1/3)Sjoerd Meijer2018-01-261-0/+8
* [ARM] Cleanup part of ARMBaseInstrInfo::optimizeCompareInstr (NFCI).Joel Galenson2018-01-221-12/+8
* [ARM] Fix perf regression in compare optimization.Joel Galenson2018-01-191-3/+2
* [ARM] Optimize {s,u}{add,sub}.with.overflow.Joel Galenson2018-01-171-23/+74
* PeepholeOptimizer: Fix for vregs without defsMatthias Braun2018-01-111-4/+10
* [CodeGen] Don't print "pred:" and "opt:" in -debug outputFrancis Visoiu Mistrih2018-01-091-3/+3
* [ARM] Fix PR35379 - incorrect unwind information when compiling with -OzMomchil Velikov2018-01-081-3/+3
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-6/+6
* [CodeGen] Print global addresses as @foo in both MIR and debug outputFrancis Visoiu Mistrih2017-12-141-1/+1
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-121-4/+13
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-5/+5
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-1/+1
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* TargetInstrInfo: Change duplicate() to work on bundles.Matthias Braun2017-08-221-13/+22
* [ARM] Adjust ifcvt heuristic for the diamond ifcvt caseJohn Brawn2017-07-121-0/+3
* [ARM] Improve if-conversion for M-class CPUs without branch predictorsJohn Brawn2017-06-281-8/+37
* Don't conditionalize Neon instructions, even in IT blocks.Kristof Beyls2017-06-221-3/+5
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [ARM] Cortex-A57 scheduling model for ARM backend (AArch32)Javed Absar2017-06-021-5/+78
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-2/+2
* Reapply r298417 "[ARM] Recommit the glueless lowering of addc/adde in Thumb1"Artyom Skrobov2017-03-221-0/+10
* Revert "[ARM] Recommit the glueless lowering of addc/adde in Thumb1, includin...Vitaly Buka2017-03-221-10/+0
* [ARM] Recommit the glueless lowering of addc/adde in Thumb1,Artyom Skrobov2017-03-211-0/+10
* [ARM] Revert r297443 and r297820.Eli Friedman2017-03-211-10/+0
* TargetInstrInfo: Provide default implementation of isTailCall().Matthias Braun2017-03-161-13/+0
* De-duplicate the two implementations of ARMBaseInstrInfo::isProfitableToIfCvt...Artyom Skrobov2017-03-141-13/+5
* For Thumb1, lower ADDC/ADDE/SUBC/SUBE via the glueless ARMISD nodes,Artyom Skrobov2017-03-101-0/+10
* Make TargetInstrInfo::isPredicable take a const reference, NFCKrzysztof Parzyszek2017-03-031-3/+3
* [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other ...Eugene Zelenko2017-01-261-29/+42
* [XRay][Arm32] Reduce the portion of the stub and implement more staging for t...Serge Rogatch2017-01-261-0/+13
* [Thumb] Add support for tMUL in the compare instruction peephole optimizer.Sjoerd Meijer2017-01-201-169/+206
* [ARM] Use helpers for adding pred / CC operands. NFCDiana Picus2017-01-201-23/+21
* [ARM] CodeGen: Remove AddDefaultCC. NFC.Diana Picus2017-01-131-10/+12
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-12/+16
* [ARM] CodeGen: Remove AddDefaultPred. NFC.Diana Picus2017-01-131-123/+155
* [Thumb] Teach ISel how to lower compares of AND bitmasks efficientlySjoerd Meijer2016-12-151-1/+5
* Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"James Molloy2016-11-031-5/+1
OpenPOWER on IntegriCloud