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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually...Owen Anderson2011-03-291-14/+0
* Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntryEvan Cheng2011-03-241-5/+12
* Cmp peephole optimization isn't always safe for signed arithmetics.Evan Cheng2011-03-231-3/+43
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-051-2/+3
* Last round of fixes for movw + movt global address codegen.Evan Cheng2011-01-211-8/+14
* Convert -enable-sched-cycles and -enable-sched-hazard to -disableAndrew Trick2011-01-211-9/+5
* Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relativeEvan Cheng2011-01-201-5/+1
* Sorry, several patches in one.Evan Cheng2011-01-201-4/+46
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-171-1/+7
* Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic.Jakob Stoklund Olesen2011-01-101-2/+1
* Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call.Evan Cheng2011-01-081-1/+0
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-3/+23
* whitespaceAndrew Trick2010-12-241-1/+1
* Remove the rest of the *_sfp Neon instruction patterns.Bob Wilson2010-12-131-2/+0
* Refactor the ARM CMPz* patterns to just use the normal CMP instructions whenJim Grosbach2010-12-071-2/+0
* Making use of VFP / NEON floating point multiply-accumulate / subtraction isEvan Cheng2010-12-051-1/+66
* Rename t2 TBB and TBH instructions to reference that they encode the jump tableJim Grosbach2010-11-291-5/+5
* Move callee-saved regs spills / reloads to TFIAnton Korobeynikov2010-11-271-122/+0
* Rewrite stack callee saved spills and restores to use push/pop instructions.Eric Christopher2010-11-181-19/+105
* Silence compiler warnings.Evan Cheng2010-11-181-2/+2
* Remove ARM isel hacks that fold large immediates into a pair of add, sub, and,Evan Cheng2010-11-171-0/+97
* Simplify code that toggle optional operand to ARM::CPSR.Evan Cheng2010-11-171-3/+3
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-80/+135
* Code clean up. The peephole pass should be the one updating the instructionEvan Cheng2010-11-151-5/+2
* Revert this temporarily.Eric Christopher2010-11-111-53/+8
* Change the prologue and epilogue to use push/pop for the low ARM registers.Eric Christopher2010-11-111-8/+53
* Two sets of changes. Sorry they are intermingled.Evan Cheng2010-11-031-38/+62
* When we look at instructions to convert to setting the 's' flag, we need to lookBill Wendling2010-11-011-4/+4
* Fix fpscr <-> GPR latency info.Evan Cheng2010-10-291-2/+9
* Avoiding overly aggressive latency scheduling. If the two nodes share anEvan Cheng2010-10-291-2/+7
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-281-5/+67
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ...Evan Cheng2010-10-281-67/+5
* - Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng2010-10-281-5/+67
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-271-3/+4
* The immediate operands of an LDRi12 instruction doesn't need the addrmode2Jim Grosbach2010-10-271-2/+6
* LDRi12 machine instructions handle negative offset operands normally (simpleJim Grosbach2010-10-271-2/+9
* Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing onJim Grosbach2010-10-271-2/+2
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-7/+14
* Use instruction itinerary to determine what instructions are 'cheap'.Evan Cheng2010-10-261-0/+15
* Move the remaining attribute macros to systematic names based on the attributeChandler Carruth2010-10-231-1/+1
* Latency between CPSR def and branch is zero.Evan Cheng2010-10-231-0/+6
* Re-enable register pressure aware machine licm with fixes. Hoist() may haveEvan Cheng2010-10-191-0/+20
* Revert r116781 "- Add a hook for target to determine whether an instruction defDaniel Dunbar2010-10-191-20/+0
* - Add a hook for target to determine whether an instruction def isEvan Cheng2010-10-191-0/+20
* Don't recompute MachineRegisterInfo in the Optimize* method.Bill Wendling2010-10-181-6/+6
* Check to make sure that the iterator isn't at the beginning of the basic blockBill Wendling2010-10-091-0/+4
* Code refactoring.Evan Cheng2010-10-071-104/+144
* Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld...Evan Cheng2010-10-071-8/+83
* Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions.Jim Grosbach2010-10-061-0/+3
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-061-0/+161
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