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path: root/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
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* [CodeGen] Print global addresses as @foo in both MIR and debug outputFrancis Visoiu Mistrih2017-12-141-1/+1
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-121-4/+13
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-5/+5
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-1/+1
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* TargetInstrInfo: Change duplicate() to work on bundles.Matthias Braun2017-08-221-13/+22
* [ARM] Adjust ifcvt heuristic for the diamond ifcvt caseJohn Brawn2017-07-121-0/+3
* [ARM] Improve if-conversion for M-class CPUs without branch predictorsJohn Brawn2017-06-281-8/+37
* Don't conditionalize Neon instructions, even in IT blocks.Kristof Beyls2017-06-221-3/+5
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [ARM] Cortex-A57 scheduling model for ARM backend (AArch32)Javed Absar2017-06-021-5/+78
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-2/+2
* Reapply r298417 "[ARM] Recommit the glueless lowering of addc/adde in Thumb1"Artyom Skrobov2017-03-221-0/+10
* Revert "[ARM] Recommit the glueless lowering of addc/adde in Thumb1, includin...Vitaly Buka2017-03-221-10/+0
* [ARM] Recommit the glueless lowering of addc/adde in Thumb1,Artyom Skrobov2017-03-211-0/+10
* [ARM] Revert r297443 and r297820.Eli Friedman2017-03-211-10/+0
* TargetInstrInfo: Provide default implementation of isTailCall().Matthias Braun2017-03-161-13/+0
* De-duplicate the two implementations of ARMBaseInstrInfo::isProfitableToIfCvt...Artyom Skrobov2017-03-141-13/+5
* For Thumb1, lower ADDC/ADDE/SUBC/SUBE via the glueless ARMISD nodes,Artyom Skrobov2017-03-101-0/+10
* Make TargetInstrInfo::isPredicable take a const reference, NFCKrzysztof Parzyszek2017-03-031-3/+3
* [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other ...Eugene Zelenko2017-01-261-29/+42
* [XRay][Arm32] Reduce the portion of the stub and implement more staging for t...Serge Rogatch2017-01-261-0/+13
* [Thumb] Add support for tMUL in the compare instruction peephole optimizer.Sjoerd Meijer2017-01-201-169/+206
* [ARM] Use helpers for adding pred / CC operands. NFCDiana Picus2017-01-201-23/+21
* [ARM] CodeGen: Remove AddDefaultCC. NFC.Diana Picus2017-01-131-10/+12
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-12/+16
* [ARM] CodeGen: Remove AddDefaultPred. NFC.Diana Picus2017-01-131-123/+155
* [Thumb] Teach ISel how to lower compares of AND bitmasks efficientlySjoerd Meijer2016-12-151-1/+5
* Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"James Molloy2016-11-031-5/+1
* [Thumb] Teach ISel how to lower compares of AND bitmasks efficientlyJames Molloy2016-11-031-1/+5
* ARM: don't rely on push/pop reglists being in order when folding SP adjust.Tim Northover2016-10-261-8/+19
* Finish renaming remaining analyzeBranch functionsMatt Arsenault2016-09-141-2/+2
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-141-2/+2
* AArch64: Use TTI branch functions in branch relaxationMatt Arsenault2016-09-141-2/+7
* Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently"James Molloy2016-09-141-5/+1
* [Thumb] Teach ISel how to lower compares of AND bitmasks efficientlyJames Molloy2016-09-131-1/+5
* Revert r281215, it caused PR30358.Nico Weber2016-09-121-5/+1
* [Thumb] Teach ISel how to lower compares of AND bitmasks efficientlyJames Molloy2016-09-121-1/+5
* [CodeGen] Split out the notions of MI invariance and MI dereferenceability.Justin Lebar2016-09-111-1/+3
* [Thumb1] Teach optimizeCompareInstr about thumb1 comparesJames Molloy2016-09-091-4/+21
* ARM: workaround bundled operation predicationSaleem Abdulrasool2016-09-061-0/+3
* [ARM] Add support for embedded position-independent codeOliver Stannard2016-08-081-0/+3
* MachineFunction: Return reference for getFrameInfo(); NFCMatthias Braun2016-07-281-2/+2
* TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFCSjoerd Meijer2016-07-281-2/+2
* [CodeGen] Take a MachineMemOperand::Flags in MachineFunction::getMachineMemOp...Justin Lebar2016-07-151-2/+2
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-151-5/+5
* ARM: Remove implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-081-5/+4
* ARM: support high registers in __builtin_longjmp on WoASaleem Abdulrasool2016-07-081-1/+2
* [ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 2 flags.Diana Picus2016-07-061-14/+4
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