| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Move size and alignment information of regclass to TargetRegisterInfo | Krzysztof Parzyszek | 2017-04-24 | 1 | -2/+2 |
| * | Reapply r298417 "[ARM] Recommit the glueless lowering of addc/adde in Thumb1" | Artyom Skrobov | 2017-03-22 | 1 | -0/+10 |
| * | Revert "[ARM] Recommit the glueless lowering of addc/adde in Thumb1, includin... | Vitaly Buka | 2017-03-22 | 1 | -10/+0 |
| * | [ARM] Recommit the glueless lowering of addc/adde in Thumb1, | Artyom Skrobov | 2017-03-21 | 1 | -0/+10 |
| * | [ARM] Revert r297443 and r297820. | Eli Friedman | 2017-03-21 | 1 | -10/+0 |
| * | TargetInstrInfo: Provide default implementation of isTailCall(). | Matthias Braun | 2017-03-16 | 1 | -13/+0 |
| * | De-duplicate the two implementations of ARMBaseInstrInfo::isProfitableToIfCvt... | Artyom Skrobov | 2017-03-14 | 1 | -13/+5 |
| * | For Thumb1, lower ADDC/ADDE/SUBC/SUBE via the glueless ARMISD nodes, | Artyom Skrobov | 2017-03-10 | 1 | -0/+10 |
| * | Make TargetInstrInfo::isPredicable take a const reference, NFC | Krzysztof Parzyszek | 2017-03-03 | 1 | -3/+3 |
| * | [ARM] Fix some Clang-tidy modernize and Include What You Use warnings; other ... | Eugene Zelenko | 2017-01-26 | 1 | -29/+42 |
| * | [XRay][Arm32] Reduce the portion of the stub and implement more staging for t... | Serge Rogatch | 2017-01-26 | 1 | -0/+13 |
| * | [Thumb] Add support for tMUL in the compare instruction peephole optimizer. | Sjoerd Meijer | 2017-01-20 | 1 | -169/+206 |
| * | [ARM] Use helpers for adding pred / CC operands. NFC | Diana Picus | 2017-01-20 | 1 | -23/+21 |
| * | [ARM] CodeGen: Remove AddDefaultCC. NFC. | Diana Picus | 2017-01-13 | 1 | -10/+12 |
| * | [CodeGen] Rename MachineInstrBuilder::addOperand. NFC | Diana Picus | 2017-01-13 | 1 | -12/+16 |
| * | [ARM] CodeGen: Remove AddDefaultPred. NFC. | Diana Picus | 2017-01-13 | 1 | -123/+155 |
| * | [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently | Sjoerd Meijer | 2016-12-15 | 1 | -1/+5 |
| * | Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently" | James Molloy | 2016-11-03 | 1 | -5/+1 |
| * | [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently | James Molloy | 2016-11-03 | 1 | -1/+5 |
| * | ARM: don't rely on push/pop reglists being in order when folding SP adjust. | Tim Northover | 2016-10-26 | 1 | -8/+19 |
| * | Finish renaming remaining analyzeBranch functions | Matt Arsenault | 2016-09-14 | 1 | -2/+2 |
| * | Make analyzeBranch family of instruction names consistent | Matt Arsenault | 2016-09-14 | 1 | -2/+2 |
| * | AArch64: Use TTI branch functions in branch relaxation | Matt Arsenault | 2016-09-14 | 1 | -2/+7 |
| * | Revert "[Thumb] Teach ISel how to lower compares of AND bitmasks efficiently" | James Molloy | 2016-09-14 | 1 | -5/+1 |
| * | [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently | James Molloy | 2016-09-13 | 1 | -1/+5 |
| * | Revert r281215, it caused PR30358. | Nico Weber | 2016-09-12 | 1 | -5/+1 |
| * | [Thumb] Teach ISel how to lower compares of AND bitmasks efficiently | James Molloy | 2016-09-12 | 1 | -1/+5 |
| * | [CodeGen] Split out the notions of MI invariance and MI dereferenceability. | Justin Lebar | 2016-09-11 | 1 | -1/+3 |
| * | [Thumb1] Teach optimizeCompareInstr about thumb1 compares | James Molloy | 2016-09-09 | 1 | -4/+21 |
| * | ARM: workaround bundled operation predication | Saleem Abdulrasool | 2016-09-06 | 1 | -0/+3 |
| * | [ARM] Add support for embedded position-independent code | Oliver Stannard | 2016-08-08 | 1 | -0/+3 |
| * | MachineFunction: Return reference for getFrameInfo(); NFC | Matthias Braun | 2016-07-28 | 1 | -2/+2 |
| * | TargetInstrInfo: rename GetInstSizeInBytes to getInstSizeInBytes. NFC | Sjoerd Meijer | 2016-07-28 | 1 | -2/+2 |
| * | [CodeGen] Take a MachineMemOperand::Flags in MachineFunction::getMachineMemOp... | Justin Lebar | 2016-07-15 | 1 | -2/+2 |
| * | Rename AnalyzeBranch* to analyzeBranch*. | Jacques Pienaar | 2016-07-15 | 1 | -5/+5 |
| * | ARM: Remove implicit iterator conversions, NFC | Duncan P. N. Exon Smith | 2016-07-08 | 1 | -5/+4 |
| * | ARM: support high registers in __builtin_longjmp on WoA | Saleem Abdulrasool | 2016-07-08 | 1 | -1/+2 |
| * | [ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 2 flags. | Diana Picus | 2016-07-06 | 1 | -14/+4 |
| * | CodeGen: Use MachineInstr& in LiveVariables API, NFC | Duncan P. N. Exon Smith | 2016-07-01 | 1 | -3/+3 |
| * | CodeGen: Use MachineInstr& in TargetInstrInfo, NFC | Duncan P. N. Exon Smith | 2016-06-30 | 1 | -484/+501 |
| * | Don't pass a Reloc::Model to GVIsIndirectSymbol. | Rafael Espindola | 2016-06-28 | 1 | -3/+1 |
| * | Don't pass Reloc::Model to places that already have it. NFC. | Rafael Espindola | 2016-06-28 | 1 | -6/+4 |
| * | [ARM] Do not test for CPUs, use SubtargetFeatures (Part 2). NFCI | Diana Picus | 2016-06-27 | 1 | -56/+63 |
| * | [ARM] Do not test for CPUs, use SubtargetFeatures (Part 1). NFCI | Diana Picus | 2016-06-23 | 1 | -3/+3 |
| * | Pass DebugLoc and SDLoc by const ref. | Benjamin Kramer | 2016-06-12 | 1 | -12/+14 |
| * | [ARM] Remove redundant check. NFC | Diana Picus | 2016-06-08 | 1 | -1/+1 |
| * | ARM: fix handling of SUB immediates in peephole opt. | Tim Northover | 2016-05-02 | 1 | -12/+30 |
| * | ARM: follow up improvements for SVN r263118 | Saleem Abdulrasool | 2016-03-10 | 1 | -0/+1 |
| * | CodeGen: Change MachineInstr to use MachineInstr&, NFC | Duncan P. N. Exon Smith | 2016-02-27 | 1 | -1/+1 |
| * | CodeGen: TII: Take MachineInstr& in predicate API, NFC | Duncan P. N. Exon Smith | 2016-02-23 | 1 | -48/+48 |
