| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". That | Evan Cheng | 2011-04-19 | 1 | -0/+202 |
| * | Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generate | Cameron Zwarich | 2011-04-15 | 1 | -1/+9 |
| * | The AND instruction leaves the V flag unmodified, so it falls victim to the same | Cameron Zwarich | 2011-04-15 | 1 | -7/+6 |
| * | Add missing register forms of instructions to the ARM CMP-folding code. This | Cameron Zwarich | 2011-04-15 | 1 | -0/+12 |
| * | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner | 2011-04-15 | 1 | -1/+1 |
| * | Fix a typo. | Cameron Zwarich | 2011-04-13 | 1 | -4/+4 |
| * | Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for ... | Owen Anderson | 2011-04-06 | 1 | -1/+8 |
| * | Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't actually... | Owen Anderson | 2011-03-29 | 1 | -14/+0 |
| * | Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry | Evan Cheng | 2011-03-24 | 1 | -5/+12 |
| * | Cmp peephole optimization isn't always safe for signed arithmetics. | Evan Cheng | 2011-03-23 | 1 | -3/+43 |
| * | Preliminary support for ARM frame save directives emission via MI flags. | Anton Korobeynikov | 2011-03-05 | 1 | -2/+3 |
| * | Last round of fixes for movw + movt global address codegen. | Evan Cheng | 2011-01-21 | 1 | -8/+14 |
| * | Convert -enable-sched-cycles and -enable-sched-hazard to -disable | Andrew Trick | 2011-01-21 | 1 | -9/+5 |
| * | Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative | Evan Cheng | 2011-01-20 | 1 | -5/+1 |
| * | Sorry, several patches in one. | Evan Cheng | 2011-01-20 | 1 | -4/+46 |
| * | Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g. | Evan Cheng | 2011-01-17 | 1 | -1/+7 |
| * | Simplify a bunch of isVirtualRegister() and isPhysicalRegister() logic. | Jakob Stoklund Olesen | 2011-01-10 | 1 | -2/+1 |
| * | Recognize inline asm 'rev /bin/bash, ' as a bswap intrinsic call. | Evan Cheng | 2011-01-08 | 1 | -1/+0 |
| * | Various bits of framework needed for precise machine-level selection | Andrew Trick | 2010-12-24 | 1 | -3/+23 |
| * | whitespace | Andrew Trick | 2010-12-24 | 1 | -1/+1 |
| * | Remove the rest of the *_sfp Neon instruction patterns. | Bob Wilson | 2010-12-13 | 1 | -2/+0 |
| * | Refactor the ARM CMPz* patterns to just use the normal CMP instructions when | Jim Grosbach | 2010-12-07 | 1 | -2/+0 |
| * | Making use of VFP / NEON floating point multiply-accumulate / subtraction is | Evan Cheng | 2010-12-05 | 1 | -1/+66 |
| * | Rename t2 TBB and TBH instructions to reference that they encode the jump table | Jim Grosbach | 2010-11-29 | 1 | -5/+5 |
| * | Move callee-saved regs spills / reloads to TFI | Anton Korobeynikov | 2010-11-27 | 1 | -122/+0 |
| * | Rewrite stack callee saved spills and restores to use push/pop instructions. | Eric Christopher | 2010-11-18 | 1 | -19/+105 |
| * | Silence compiler warnings. | Evan Cheng | 2010-11-18 | 1 | -2/+2 |
| * | Remove ARM isel hacks that fold large immediates into a pair of add, sub, and, | Evan Cheng | 2010-11-17 | 1 | -0/+97 |
| * | Simplify code that toggle optional operand to ARM::CPSR. | Evan Cheng | 2010-11-17 | 1 | -3/+3 |
| * | Encode the multi-load/store instructions with their respective modes ('ia', | Bill Wendling | 2010-11-16 | 1 | -80/+135 |
| * | Code clean up. The peephole pass should be the one updating the instruction | Evan Cheng | 2010-11-15 | 1 | -5/+2 |
| * | Revert this temporarily. | Eric Christopher | 2010-11-11 | 1 | -53/+8 |
| * | Change the prologue and epilogue to use push/pop for the low ARM registers. | Eric Christopher | 2010-11-11 | 1 | -8/+53 |
| * | Two sets of changes. Sorry they are intermingled. | Evan Cheng | 2010-11-03 | 1 | -38/+62 |
| * | When we look at instructions to convert to setting the 's' flag, we need to look | Bill Wendling | 2010-11-01 | 1 | -4/+4 |
| * | Fix fpscr <-> GPR latency info. | Evan Cheng | 2010-10-29 | 1 | -2/+9 |
| * | Avoiding overly aggressive latency scheduling. If the two nodes share an | Evan Cheng | 2010-10-29 | 1 | -2/+7 |
| * | Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. | Evan Cheng | 2010-10-28 | 1 | -5/+67 |
| * | Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ... | Evan Cheng | 2010-10-28 | 1 | -67/+5 |
| * | - Assign load / store with shifter op address modes the right itinerary classes. | Evan Cheng | 2010-10-28 | 1 | -5/+67 |
| * | Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like | Jim Grosbach | 2010-10-27 | 1 | -3/+4 |
| * | The immediate operands of an LDRi12 instruction doesn't need the addrmode2 | Jim Grosbach | 2010-10-27 | 1 | -2/+6 |
| * | LDRi12 machine instructions handle negative offset operands normally (simple | Jim Grosbach | 2010-10-27 | 1 | -2/+9 |
| * | Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on | Jim Grosbach | 2010-10-27 | 1 | -2/+2 |
| * | First part of refactoring ARM addrmode2 (load/store) instructions to be more | Jim Grosbach | 2010-10-26 | 1 | -7/+14 |
| * | Use instruction itinerary to determine what instructions are 'cheap'. | Evan Cheng | 2010-10-26 | 1 | -0/+15 |
| * | Move the remaining attribute macros to systematic names based on the attribute | Chandler Carruth | 2010-10-23 | 1 | -1/+1 |
| * | Latency between CPSR def and branch is zero. | Evan Cheng | 2010-10-23 | 1 | -0/+6 |
| * | Re-enable register pressure aware machine licm with fixes. Hoist() may have | Evan Cheng | 2010-10-19 | 1 | -0/+20 |
| * | Revert r116781 "- Add a hook for target to determine whether an instruction def | Daniel Dunbar | 2010-10-19 | 1 | -20/+0 |
