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path: root/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
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* Remove unnecessary default cases in switches that cover all enum values.David Blaikie2012-01-101-1/+0
| | | | llvm-svn: 147855
* Implement 'e' and 'f' modifiers for Neon inline asm. <rdar://problem/10551006>Bob Wilson2011-12-121-4/+14
| | | | | | | | | These modifiers simply select either the low or high D subregister of a Neon Q register. I've also removed the unimplemented 'p' modifier, which turns out to be a bit different than the comment here suggests and as far as I can tell was only intended for internal use in Apple's version of gcc. llvm-svn: 146417
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-1/+1
| | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. llvm-svn: 146026
* Align ARM constant pool islands via their basic block.Jakob Stoklund Olesen2011-12-061-2/+1
| | | | | | | | | | | Previously, all ARM::CONSTPOOL_ENTRY instructions had a hardwired alignment of 4 bytes emitted by ARMAsmPrinter. Now the same alignment is set on the basic block. This is in preparation of supporting ARM constant pool islands with different alignments. llvm-svn: 145890
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-4/+3
| | | | | | | | | | | | change, now you need a TargetOptions object to create a TargetMachine. Clang patch to follow. One small functionality change in PTX. PTX had commented out the machine verifier parts in their copy of printAndVerify. That now calls the version in LLVMTargetMachine. Users of PTX who need verification disabled should rely on not passing the command-line flag to enable it. llvm-svn: 145714
* Replace (Lower|Upper)caseString in favor of StringRef's newest methods.Benjamin Kramer2011-11-061-4/+3
| | | | llvm-svn: 143891
* Teach the MC to output code/data region marker labels in MachO and ELF ↵Owen Anderson2011-10-041-1/+20
| | | | | | modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment. llvm-svn: 141135
* Use the ARMConstantPoolMBB class to handle the MBB values.Bill Wendling2011-10-011-1/+1
| | | | llvm-svn: 140943
* Use the new ARMConstantPoolSymbol class to handle external symbols.Bill Wendling2011-10-011-1/+2
| | | | llvm-svn: 140939
* Switch over to using ARMConstantPoolConstant for global variables, functions,Bill Wendling2011-10-011-2/+4
| | | | | | and block addresses. llvm-svn: 140936
* Create a machine basic block in the constant pool and retrieve the symbol ↵Bill Wendling2011-09-291-0/+3
| | | | | | for an MBB. llvm-svn: 140824
* Lower ARM adds/subs to add/sub after adding optional CPSR operand.Andrew Trick2011-09-211-0/+3
| | | | | | | | | | | | | This is still a hack until we can teach tblgen to generate the optional CPSR operand rather than an implicit CPSR def. But the strangeness is now limited to the selection DAG. ADD/SUB MI's no longer have implicit CPSR defs, nor do we allow flag setting variants of these opcodes in machine code. There are several corner cases to consider, and getting one wrong would previously lead to nasty miscompilation. It's not the first time I've debugged one, so this time I added enough verification to ensure it won't happen again. llvm-svn: 140228
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-091-0/+4
| | | | | | have a predicate operand, unlike conditional branches. llvm-svn: 139415
* Tidy up. Formatting.Jim Grosbach2011-09-021-9/+10
| | | | llvm-svn: 139024
* Static relocation model Thumb jump table interworking.Jim Grosbach2011-08-311-0/+5
| | | | | | | Make sure the low bit of the PC is set when loading an address directly for jump tables in static relocation model. llvm-svn: 138912
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | These are strictly utilities for registering targets and components. llvm-svn: 138450
* Move ARM frame-unwinding EHABI handling a touch earlier.Jim Grosbach2011-08-231-4/+4
| | | | | | | | It should go before AsmPrinter MC pseudo expansion since it's based on MachineInstr, not MCInst. Otherwise any frame related pseudo instructions may be missed. llvm-svn: 138386
* Add support for the R and Q constraints.Rafael Espindola2011-08-101-2/+22
| | | | llvm-svn: 137217
* Emitting ARM build attributes and values as ULEB, rather than char.Renato Golin2011-08-091-11/+67
| | | | llvm-svn: 137115
* Split am2offset into register addend and immediate addend forms, necessary ↵Owen Anderson2011-07-261-1/+2
| | | | | | for allowing the fixed-length disassembler to distinguish between SBFX and STR_PRE. llvm-svn: 136141
* Separate MCInstPrinter registration from AsmPrinter registration.Evan Cheng2011-07-251-11/+0
| | | | llvm-svn: 135974
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-2/+2
| | | | | | ARM MC code from target. llvm-svn: 135636
* Use tPseudoExpand for tTAILJMPrND and tTAILJMPr.Jim Grosbach2011-07-081-14/+0
| | | | llvm-svn: 134734
* Use tPseudoExpand for tTAILJMPd and tTAILJMPdND.Jim Grosbach2011-07-081-12/+0
| | | | llvm-svn: 134732
* Use ARMPseudoExpand for ARM tail calls.Jim Grosbach2011-07-081-19/+1
| | | | llvm-svn: 134719
* Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.Jim Grosbach2011-07-081-18/+0
| | | | | | TableGen'erated MC lowering pseudo-expansion. llvm-svn: 134712
* Use TableGen'erated pseudo lowering for ARM.Jim Grosbach2011-07-081-85/+9
| | | | | | | | | Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
* The VMLA instruction and its friends are not actually fused; they're plain oldCameron Zwarich2011-07-071-1/+1
| | | | | | multiply-accumulate instructions with separate rounding steps. llvm-svn: 134609
* createMCInstPrinter doesn't need TargetMachine anymore.Evan Cheng2011-07-061-2/+1
| | | | llvm-svn: 134525
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-301-7/+5
| | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. llvm-svn: 134204
* Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-301-2/+6
| | | | | | | | | Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. llvm-svn: 134197
* Pseudo-ize the t2LDMIA_RET instruction.Jim Grosbach2011-06-301-0/+8
| | | | | | | | It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. llvm-svn: 134173
* Pseudo-ize the Thumb tPOP_RET instruction.Jim Grosbach2011-06-301-0/+8
| | | | | | | It's just a tPOP instruction with additional code-gen properties, so it doesn't need encoding information. llvm-svn: 134172
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-291-10/+2
| | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. llvm-svn: 134114
* Implement the 'M' output modifier for arm inline asm. This is fairlyEric Christopher2011-05-281-2/+27
| | | | | | | | | register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
* Make size computation less brittle.Rafael Espindola2011-05-271-39/+0
| | | | llvm-svn: 132222
* Reorganize these slightly according to operand type.Eric Christopher2011-05-261-2/+2
| | | | llvm-svn: 132128
* Mark tBX as an indirect branch rather than a return.Cameron Zwarich2011-05-261-1/+1
| | | | llvm-svn: 132107
* Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.Cameron Zwarich2011-05-251-0/+20
| | | | llvm-svn: 132086
* Implement the 'm' modifier. Note that it only works for memory operands.Eric Christopher2011-05-251-4/+14
| | | | | | Part of rdar://9119939 llvm-svn: 132081
* Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. ThisCameron Zwarich2011-05-251-1/+1
| | | | | | fixes <rdar://problem/9495913> llvm-svn: 132042
* Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to betterCameron Zwarich2011-05-251-1/+1
| | | | | | reflect their actual meaning and match the ARM instructions. llvm-svn: 132039
* Implement the arm 'L' asm modifier.Eric Christopher2011-05-241-1/+5
| | | | | | Part of rdar://9119939 llvm-svn: 132024
* Implement the immediate part of the 'B' modifier.Eric Christopher2011-05-241-0/+4
| | | | | | Part of rdar://9119939 llvm-svn: 132023
* Add more unimplemented asm modifiers and some documentation of what theyEric Christopher2011-05-241-3/+13
| | | | | | | | do. Part of rdar://9119939. llvm-svn: 132015
* Add support for the arm 'y' asm modifier.Eric Christopher2011-05-241-0/+12
| | | | | | Fixes part of rdar://9444657 llvm-svn: 132011
* Fix <rdar://problem/9476260> by having tail calls always generate 32-bit ↵Cameron Zwarich2011-05-231-1/+3
| | | | | | | | branches in Darwin Thumb2 code. Tail calls are already disabled on Thumb1. llvm-svn: 131894
* adds some attributes to attribute section when cpu is "xscale"Rafael Espindola2011-05-201-0/+6
| | | | | | | | (this is what used in Android NDK, when architecture is ARMv5) patch by Koan-Sin Tan llvm-svn: 131751
* sets bit 0 of the function address of thumb function in .symtabRafael Espindola2011-05-161-1/+1
| | | | | | | | | | ("T is 1 if the target symbol S has type STT_FUNC and the symbol addresses a Thumb instruction ;it is 0 otherwise." from "ELF for the ARM Architecture" 4.7.1.2) Patch by Koan-Sin Tan! llvm-svn: 131406
* Do not emit location expression size twice.Devang Patel2011-05-041-12/+0
| | | | llvm-svn: 130854
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