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authorCameron Zwarich <zwarich@apple.com>2011-05-25 21:53:50 +0000
committerCameron Zwarich <zwarich@apple.com>2011-05-25 21:53:50 +0000
commita946f476d3d55210a782f49136c12f92d9458d30 (patch)
treef8a250d523a37b1a3beadad500c7d5119230b3fb /llvm/lib/Target/ARM/ARMAsmPrinter.cpp
parent2f6ecea19d3d5380e7c34502138e44b96476856e (diff)
downloadbcm5719-llvm-a946f476d3d55210a782f49136c12f92d9458d30.tar.gz
bcm5719-llvm-a946f476d3d55210a782f49136c12f92d9458d30.zip
Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.
llvm-svn: 132086
Diffstat (limited to 'llvm/lib/Target/ARM/ARMAsmPrinter.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMAsmPrinter.cpp20
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
index 41cedab9692..ca1463083b4 100644
--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1222,6 +1222,26 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
}
return;
}
+ case ARM::tBXr9_CALL:
+ case ARM::tBX_CALL: {
+ {
+ MCInst TmpInst;
+ TmpInst.setOpcode(ARM::tMOVr);
+ TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
+ TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
+ OutStreamer.EmitInstruction(TmpInst);
+ }
+ {
+ MCInst TmpInst;
+ TmpInst.setOpcode(ARM::tBX);
+ TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
+ // Add predicate operands.
+ TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+ TmpInst.addOperand(MCOperand::CreateReg(0));
+ OutStreamer.EmitInstruction(TmpInst);
+ }
+ return;
+ }
case ARM::BMOVPCRXr9_CALL:
case ARM::BMOVPCRX_CALL: {
{
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