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path: root/llvm/lib/Target/ARM/ARMAsmPrinter.cpp
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* Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred.Jim Grosbach2011-07-081-18/+0
| | | | | | TableGen'erated MC lowering pseudo-expansion. llvm-svn: 134712
* Use TableGen'erated pseudo lowering for ARM.Jim Grosbach2011-07-081-85/+9
| | | | | | | | | Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. llvm-svn: 134705
* The VMLA instruction and its friends are not actually fused; they're plain oldCameron Zwarich2011-07-071-1/+1
| | | | | | multiply-accumulate instructions with separate rounding steps. llvm-svn: 134609
* createMCInstPrinter doesn't need TargetMachine anymore.Evan Cheng2011-07-061-2/+1
| | | | llvm-svn: 134525
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-301-7/+5
| | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. llvm-svn: 134204
* Thumb1 register to register MOV instruction is predicable.Jim Grosbach2011-06-301-2/+6
| | | | | | | | | Fix a FIXME and allow predication (in Thumb2) for the T1 register to register MOV instructions. This allows some better codegen with if-conversion (as seen in the test updates), plus it lays the groundwork for pseudo-izing the tMOVCC instructions. llvm-svn: 134197
* Pseudo-ize the t2LDMIA_RET instruction.Jim Grosbach2011-06-301-0/+8
| | | | | | | | It's just a t2LDMIA_UPD instruction with extra codegen properties, so it doesn't need the encoding information. As a side-benefit, we now correctly recognize for instruction printing as a 'pop' instruction. llvm-svn: 134173
* Pseudo-ize the Thumb tPOP_RET instruction.Jim Grosbach2011-06-301-0/+8
| | | | | | | It's just a tPOP instruction with additional code-gen properties, so it doesn't need encoding information. llvm-svn: 134172
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-291-10/+2
| | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. llvm-svn: 134114
* Implement the 'M' output modifier for arm inline asm. This is fairlyEric Christopher2011-05-281-2/+27
| | | | | | | | | register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
* Make size computation less brittle.Rafael Espindola2011-05-271-39/+0
| | | | llvm-svn: 132222
* Reorganize these slightly according to operand type.Eric Christopher2011-05-261-2/+2
| | | | llvm-svn: 132128
* Mark tBX as an indirect branch rather than a return.Cameron Zwarich2011-05-261-1/+1
| | | | llvm-svn: 132107
* Convert tBX_CALL / tBXr9_CALL to actual pseudoinstructions.Cameron Zwarich2011-05-251-0/+20
| | | | llvm-svn: 132086
* Implement the 'm' modifier. Note that it only works for memory operands.Eric Christopher2011-05-251-4/+14
| | | | | | Part of rdar://9119939 llvm-svn: 132081
* Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. ThisCameron Zwarich2011-05-251-1/+1
| | | | | | fixes <rdar://problem/9495913> llvm-svn: 132042
* Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to betterCameron Zwarich2011-05-251-1/+1
| | | | | | reflect their actual meaning and match the ARM instructions. llvm-svn: 132039
* Implement the arm 'L' asm modifier.Eric Christopher2011-05-241-1/+5
| | | | | | Part of rdar://9119939 llvm-svn: 132024
* Implement the immediate part of the 'B' modifier.Eric Christopher2011-05-241-0/+4
| | | | | | Part of rdar://9119939 llvm-svn: 132023
* Add more unimplemented asm modifiers and some documentation of what theyEric Christopher2011-05-241-3/+13
| | | | | | | | do. Part of rdar://9119939. llvm-svn: 132015
* Add support for the arm 'y' asm modifier.Eric Christopher2011-05-241-0/+12
| | | | | | Fixes part of rdar://9444657 llvm-svn: 132011
* Fix <rdar://problem/9476260> by having tail calls always generate 32-bit ↵Cameron Zwarich2011-05-231-1/+3
| | | | | | | | branches in Darwin Thumb2 code. Tail calls are already disabled on Thumb1. llvm-svn: 131894
* adds some attributes to attribute section when cpu is "xscale"Rafael Espindola2011-05-201-0/+6
| | | | | | | | (this is what used in Android NDK, when architecture is ARMv5) patch by Koan-Sin Tan llvm-svn: 131751
* sets bit 0 of the function address of thumb function in .symtabRafael Espindola2011-05-161-1/+1
| | | | | | | | | | ("T is 1 if the target symbol S has type STT_FUNC and the symbol addresses a Thumb instruction ;it is 0 otherwise." from "ELF for the ARM Architecture" 4.7.1.2) Patch by Koan-Sin Tan! llvm-svn: 131406
* Do not emit location expression size twice.Devang Patel2011-05-041-12/+0
| | | | llvm-svn: 130854
* Teach dwarf writer to handle complex address expression for .debug_loc entries.Devang Patel2011-04-281-0/+41
| | | | | | | This fixes clang generated blocks' variables' debug info. Radar 9279956. llvm-svn: 130373
* Revert r130178. It turned out to be not the optimal path to emit complex ↵Devang Patel2011-04-271-6/+4
| | | | | | location expressions. llvm-svn: 130326
* Let dwarf writer allocate extra space in the debug location expression. This ↵Devang Patel2011-04-261-4/+6
| | | | | | space, if requested, will be used for complex addresses of the Blocks' variables. llvm-svn: 130178
* Add asserts.Devang Patel2011-04-221-0/+2
| | | | llvm-svn: 129995
* Fix DWARF description of Q registers.Devang Patel2011-04-211-0/+27
| | | | llvm-svn: 129952
* Fix DWARF description of S registers.Devang Patel2011-04-211-0/+41
| | | | llvm-svn: 129947
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | Luis Felipe Strano Moraes! llvm-svn: 129558
* We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling2011-03-211-1/+2
| | | | | | | | | the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. llvm-svn: 127986
* Clean up ARM tail calls a bit. They're pseudo-instructions for normal branches.Jim Grosbach2011-03-151-0/+43
| | | | | | | Also more cleanly separate the ARM vs. Thumb functionality. Previously, the encoding would be incorrect for some Thumb instructions (the indirect calls). llvm-svn: 127637
* Pseudo-ize the ARM Darwin *r9 call instruction definitions. They're the sameJim Grosbach2011-03-121-0/+20
| | | | | | | | actual instruction as the non-Darwin defs, but have different call-clobber semantics and so need separate patterns. They don't need to duplicate the encoding information, however. llvm-svn: 127515
* Pseudo-ize the ARM 'B' instruction.Jim Grosbach2011-03-111-0/+11
| | | | llvm-svn: 127510
* Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side-Jim Grosbach2011-03-111-0/+10
| | | | | | effect that we get proper instruction printing using the "pop" mnemonic for it. llvm-svn: 127502
* ARM assembler stuff is crazy: for .setfp positive values of offset ↵Anton Korobeynikov2011-03-051-3/+4
| | | | | | corresponds to "add" instruction, not to "sub" as in .pad case llvm-svn: 127106
* In Thumb1 mode the constant might be materialized via the load from ↵Anton Korobeynikov2011-03-051-2/+16
| | | | | | constpool. Emit unwinding information in case when this load from constpool is used to change the stack pointer in the prologue. llvm-svn: 127105
* Implement frame unwinding information emission for Thumb1. Not finished yet ↵Anton Korobeynikov2011-03-051-3/+11
| | | | | | because there is no way given the constpool index to examine the actual entry: the reason is clones inserted by constant island pass, which are not tracked at all! The only connection is done during asmprinting time via magic label names which is really gross and needs to be eventually fixed. llvm-svn: 127104
* Add unwind information emission for thumb stuffAnton Korobeynikov2011-03-051-3/+29
| | | | llvm-svn: 127103
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-051-0/+86
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. llvm-svn: 127101
* Fixing a bug when printing fpu text to object file. Patch by Mans Rullgard.Renato Golin2011-03-021-1/+1
| | | | llvm-svn: 126882
* Fix .fpu printing in ARM assembly, regarding bug ↵Renato Golin2011-02-281-4/+38
| | | | | | http://llvm.org/bugs/show_bug.cgi?id=8931 llvm-svn: 126689
* ARM/MC/ELF Lowercase .cpu attributes in .s, but make them uppercase in .oJason W Kim2011-02-071-3/+3
| | | | llvm-svn: 125025
* Rework some .ARM.attribute work for improved gcc compatibility.Jason W Kim2011-02-071-13/+50
| | | | | | | Unified EmitTextAttribute for both Asm and Obj emission (.cpu only) Added necessary cortex-A8 related attrs for codegen compat tests. llvm-svn: 124995
* Last round of fixes for movw + movt global address codegen.Evan Cheng2011-01-211-24/+42
| | | | | | | | | | 1. Fixed ARM pc adjustment. 2. Fixed dynamic-no-pic codegen 3. CSE of pc-relative load of global addresses. It's now enabled by default for Darwin. llvm-svn: 123991
* Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.Evan Cheng2011-01-171-18/+78
| | | | | | | | | | | | movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4)) movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4)) LPC0_0: add r0, pc, r0 It's not yet enabled by default as some tests are failing. I suspect bugs in down stream tools. llvm-svn: 123619
* JimG sez: "The value-kinds look like masks, but they're not consistently usedJason W Kim2011-01-121-2/+2
| | | | | | | | | | | that way, unfortunately. If you want to change them to work additively instead of a one-variant-kind-per-symbolref, that's great and I completely agree it's worth doing, but it really should be a separate patch. Until then, this isn't correct." So I am reverting this bit until a more opportune time. llvm-svn: 123340
* 1. Support ELF pcrel relocations for movw/movt:Jason W Kim2011-01-121-2/+2
| | | | | | | | R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC. 2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum. 3. Add support for 3 new elf section types (no-ops) llvm-svn: 123294
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