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* rename LowerToMCInst -> LowerARMMachineInstrToMCInst.Chris Lattner2010-11-141-1/+2
| | | | llvm-svn: 119071
* even more simplifications. ARM MCInstLowering is now justChris Lattner2010-11-141-0/+5
| | | | | | | a single function instead of a class. It doesn't need the complexity that X86 does. llvm-svn: 119070
* I added a new file ARMAsmBackend which stubs out in similar ways toJason W Kim2010-09-301-0/+3
| | | | | | | | | | the eqv X86 class. For now, I split the ELFARMAsmBackend from the DarwinARMAsmBackend (also mimicking X86) Tested against -r115126 llvm-svn: 115129
* Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!Jim Grosbach2010-09-171-0/+5
| | | | llvm-svn: 114195
* Factor out basic enums and hleper functions from ARM.h for cleaner sharingJim Grosbach2010-09-151-101/+1
| | | | | | between the compiler back end and the MC libraries. llvm-svn: 114007
* Convert some VTBL and VTBX instructions to use pseudo instructions prior toBob Wilson2010-09-131-1/+0
| | | | | | | register allocation. Remove the NEONPreAllocPass, which is no longer needed. Yeah!! llvm-svn: 113818
* Add comments for what the condition code symbols mean.Bill Wendling2010-08-241-16/+16
| | | | llvm-svn: 111889
* Cleaned up the for-disassembly-only entries in the arm instruction table so thatJohnny Chen2010-08-121-0/+27
| | | | | | | the memory barrier variants (other than 'SY' full system domain read and write) are treated as one instruction with option operand. llvm-svn: 110951
* Hook in GlobalMerge passAnton Korobeynikov2010-07-241-0/+1
| | | | llvm-svn: 109359
* Remove early IT block formation. It's not used.Evan Cheng2010-07-021-1/+1
| | | | llvm-svn: 107513
* Remove the hidden "neon-reg-sequence" option. The reg sequences are workingBob Wilson2010-06-161-4/+0
| | | | | | now, so there's no need to disable them. llvm-svn: 106155
* Thumb2 IT blocks are fairly expensive. When there are multiple selects usingEvan Cheng2010-06-091-1/+1
| | | | | | | | | | | | | | | the same condition, it's important to make sure they are scheduled together to avoid forming multiple IT blocks. I'm adding a pre-regalloc pass that forms IT blocks early (by re-scheduling instructions and split basic blocks) to attempt to fix this. This is not turned on by default since I am not sure this is the right fix. Another issue is llvm selects are modeled as two-address conditional moves. This can be very bad when the copies before the conditional moves are not coalesced away. Teach IT formation pass to move the copies above the IT block (when legal) to avoid breaking the IT block. llvm-svn: 105669
* Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE.Evan Cheng2010-05-051-2/+6
| | | | llvm-svn: 103104
* Remove late ARM codegen optimization pass committed by accident.Anton Korobeynikov2010-04-071-1/+0
| | | | | | It is not ready for public yet. llvm-svn: 100673
* Some initial version of global mergerAnton Korobeynikov2010-04-071-0/+1
| | | | llvm-svn: 100641
* tidy some targets.Chris Lattner2010-02-021-2/+0
| | | | llvm-svn: 95146
* remove dead code.Chris Lattner2010-02-021-4/+0
| | | | llvm-svn: 95134
* Factor the stack alignment calculations out into a target independent pass.Jim Grosbach2009-12-021-1/+0
| | | | | | No functionality change. llvm-svn: 90336
* Detect need for autoalignment of the stack earlier to catch spills moreJim Grosbach2009-11-151-0/+1
| | | | | | | conservatively. eliminateFrameIndex() machinery adjust to handle addr mode 6 (vld1/vst1) used for spills. Fix tests to expect aligned Q-reg spilling llvm-svn: 88874
* - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng2009-11-061-0/+1
| | | | | | | | | | | | load of a GV from constantpool and then add pc. It allows the code sequence to be rematerializable so it would be hoisted by machine licm. - Add a late pass to break these pseudo instructions into a number of real instructions. Also move the code in Thumb2 IT pass that breaks up t2MOVi32imm to this pass. This is done before post regalloc scheduling to allow the scheduler to proper schedule these instructions. It also allow them to be if-converted and shrunk by later passes. llvm-svn: 86304
* Turn neon reg-reg moves fixup code into separate pass. This should reduce ↵Anton Korobeynikov2009-11-031-0/+1
| | | | | | the compile time. llvm-svn: 85850
* Pass the optimization level when constructing the ARM instruction selector.Bob Wilson2009-09-281-1/+2
| | | | | | | Otherwise, it is always set to "default", which prevents debug info from even being generated during isel. Radar 7250345. llvm-svn: 82988
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-1/+1
| | | | llvm-svn: 78666
* Code refactoring. No functionality change.Evan Cheng2009-08-081-0/+1
| | | | llvm-svn: 78455
* Add a new pre-allocation pass to assign adjacent registers for Neon instructionsBob Wilson2009-08-051-1/+1
| | | | | | | | | that have that constraint. This is currently just assigning a fixed set of registers, and it only handles VLDn for n=2,3,4 with DPR registers. I'm going to expand it to handle more operations next; we can make it smarter once everything is working correctly. llvm-svn: 78256
* Remove a redundant declaration.Bob Wilson2009-08-051-2/+0
| | | | llvm-svn: 78216
* Add new helpers for registering targets.Daniel Dunbar2009-07-251-3/+0
| | | | | | - Less boilerplate == good. llvm-svn: 77052
* Put Target definitions inside Target specific header, and llvm namespace.Daniel Dunbar2009-07-181-0/+2
| | | | llvm-svn: 76344
* Reapply TargetRegistry refactoring commits.Daniel Dunbar2009-07-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | --- Reverse-merging r75799 into '.': U test/Analysis/PointerTracking U include/llvm/Target/TargetMachineRegistry.h U include/llvm/Target/TargetMachine.h U include/llvm/Target/TargetRegistry.h U include/llvm/Target/TargetSelect.h U tools/lto/LTOCodeGenerator.cpp U tools/lto/LTOModule.cpp U tools/llc/llc.cpp U lib/Target/PowerPC/PPCTargetMachine.h U lib/Target/PowerPC/AsmPrinter/PPCAsmPrinter.cpp U lib/Target/PowerPC/PPCTargetMachine.cpp U lib/Target/PowerPC/PPC.h U lib/Target/ARM/ARMTargetMachine.cpp U lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp U lib/Target/ARM/ARMTargetMachine.h U lib/Target/ARM/ARM.h U lib/Target/XCore/XCoreTargetMachine.cpp U lib/Target/XCore/XCoreTargetMachine.h U lib/Target/PIC16/PIC16TargetMachine.cpp U lib/Target/PIC16/PIC16TargetMachine.h U lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp U lib/Target/Alpha/AlphaTargetMachine.cpp U lib/Target/Alpha/AlphaTargetMachine.h U lib/Target/X86/X86TargetMachine.h U lib/Target/X86/X86.h U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86AsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86TargetMachine.cpp U lib/Target/MSP430/MSP430TargetMachine.cpp U lib/Target/MSP430/MSP430TargetMachine.h U lib/Target/CppBackend/CPPTargetMachine.h U lib/Target/CppBackend/CPPBackend.cpp U lib/Target/CBackend/CTargetMachine.h U lib/Target/CBackend/CBackend.cpp U lib/Target/TargetMachine.cpp U lib/Target/IA64/IA64TargetMachine.cpp U lib/Target/IA64/AsmPrinter/IA64AsmPrinter.cpp U lib/Target/IA64/IA64TargetMachine.h U lib/Target/IA64/IA64.h U lib/Target/MSIL/MSILWriter.cpp U lib/Target/CellSPU/SPUTargetMachine.h U lib/Target/CellSPU/SPU.h U lib/Target/CellSPU/AsmPrinter/SPUAsmPrinter.cpp U lib/Target/CellSPU/SPUTargetMachine.cpp U lib/Target/Mips/AsmPrinter/MipsAsmPrinter.cpp U lib/Target/Mips/MipsTargetMachine.cpp U lib/Target/Mips/MipsTargetMachine.h U lib/Target/Mips/Mips.h U lib/Target/Sparc/AsmPrinter/SparcAsmPrinter.cpp U lib/Target/Sparc/SparcTargetMachine.cpp U lib/Target/Sparc/SparcTargetMachine.h U lib/ExecutionEngine/JIT/TargetSelect.cpp U lib/Support/TargetRegistry.cpp llvm-svn: 75820
* Revert 75762, 75763, 75766..75769, 75772..75775, 75778, 75780, 75782 to ↵Stuart Hastings2009-07-151-1/+1
| | | | | | | | repair broken LLVM-GCC build. Will revert 75770 in the llvm-gcc trunk. llvm-svn: 75799
* Register Target's TargetMachine and AsmPrinter in the new registry.Daniel Dunbar2009-07-151-1/+1
| | | | | | | - This abuses TargetMachineRegistry's constructor for now, this will get cleaned up in time. llvm-svn: 75762
* Have asm printers use formatted_raw_ostream directly to avoid aDavid Greene2009-07-141-2/+2
| | | | | | dynamic_cast<>. llvm-svn: 75670
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-2/+2
| | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). llvm-svn: 75640
* assert(0) -> LLVM_UNREACHABLE.Torok Edwin2009-07-111-2/+3
| | | | | | | | | Make llvm_unreachable take an optional string, thus moving the cerr<< out of line. LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for NDEBUG builds. llvm-svn: 75379
* Add a thumb2 pass to insert IT blocks.Evan Cheng2009-07-101-0/+2
| | | | llvm-svn: 75218
* Add the Object Code Emitter class. Original patch by Aaron Gray, I did someBruno Cardoso Lopes2009-07-061-0/+3
| | | | | | cleanup, removed some #includes and moved Object Code Emitter out-of-line. llvm-svn: 74813
* Remove unused AsmPrinter OptLevel argument, and propogate.Daniel Dunbar2009-07-011-1/+0
| | | | | | | - This more or less amounts to a revert of r65379. I'm curious to know what happened that caused this variable to become unused. llvm-svn: 74579
* Split thumb-related stuff into separate classes.Anton Korobeynikov2009-06-261-9/+9
| | | | | | Step 1: ARMInstructionInfo => {ARM,Thumb}InstructionInfo llvm-svn: 74329
* Add a ARM specific pre-allocation pass that re-schedule loads / stores fromEvan Cheng2009-06-131-5/+5
| | | | | | | | | | | consecutive addresses togther. This makes it easier for the post-allocation pass to form ldm / stm. This is step 1. We are still missing a lot of ldm / stm opportunities because of register allocation are not done in the desired order. More enhancements coming. llvm-svn: 73291
* Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron GrayBruno Cardoso Lopes2009-06-011-9/+4
| | | | llvm-svn: 72697
* First patch in the direction of splitting MachineCodeEmitter in two subclasses:Bruno Cardoso Lopes2009-05-301-0/+12
| | | | | | JITCodeEmitter and ObjectCodeEmitter. No functional changes yet. Patch by Aaron Gray llvm-svn: 72631
* Instead of passing in an unsigned value for the optimization level, use an enum,Bill Wendling2009-04-291-1/+3
| | | | | | | which better identifies what the optimization is doing. And is more flexible for future uses. llvm-svn: 70440
* Second attempt:Bill Wendling2009-04-291-1/+1
| | | | | | | | | | | | Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want to use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'll change the JIT with a follow-up patch. llvm-svn: 70343
* r70270 isn't ready yet. Back this out. Sorry for the noise.Bill Wendling2009-04-281-1/+1
| | | | llvm-svn: 70275
* Massive check in. This changes the "-fast" flag to "-O#" in llc. If you want toBill Wendling2009-04-281-1/+1
| | | | | | | | | | | use the old behavior, the flag is -O0. This change allows for finer-grained control over which optimizations are run at different -O levels. Most of this work was pretty mechanical. The majority of the fixes came from verifying that a "fast" variable wasn't used anymore. The JIT still uses a "Fast" flag. I'm not 100% sure if it's necessary to change it there... llvm-svn: 70270
* CodeGen still defaults to non-verbose asm, but llc now overrides it and ↵Evan Cheng2009-03-251-1/+1
| | | | | | default to verbose. llvm-svn: 67668
* Overhaul my earlier submission due to feedback. It's a large patch, but most ofBill Wendling2009-02-241-1/+3
| | | | | | | | | | | | them are generic changes. - Use the "fast" flag that's already being passed into the asm printers instead of shoving it into the DwarfWriter. - Instead of calling "MI->getParent()->getParent()" for every MI, set the machine function when calling "runOnMachineFunction" in the asm printers. llvm-svn: 65379
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-051-1/+0
| | | | llvm-svn: 61715
* Comment to be explicit that the enumeration values for CondCodes matter.Jim Grosbach2008-10-081-0/+2
| | | | llvm-svn: 57295
* Use raw_ostream throughout the AsmPrinter.Owen Anderson2008-08-211-1/+2
| | | | llvm-svn: 55092
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