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* [Alignment][NFC] Remove LogAlignment functionsGuillaume Chatelet2019-09-181-1/+1
| | | | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, jrtc27, MaskRay, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67620 llvm-svn: 372231
* [AMDGPU] Allow FP inline constant in v_madak_f16 and v_fmaak_f16Tim Renouf2019-09-181-1/+3
| | | | | | | Differential Revision: https://reviews.llvm.org/D67680 Change-Id: Ic38f47cb2079c2c1070a441b5943854844d80a7c llvm-svn: 372208
* [AMDGPU] Added MI bit IsDOTStanislav Mekhanoshin2019-09-176-2/+22
| | | | | | | | NFC, needed for future commit. Differential Revision: https://reviews.llvm.org/D67669 llvm-svn: 372151
* [SVE][MVT] Fixed-length vector MVT rangesGraham Hunter2019-09-171-1/+1
| | | | | | | | | | | | | | | | | * Reordered MVT simple types to group scalable vector types together. * New range functions in MachineValueType.h to only iterate over the fixed-length int/fp vector types. * Stopped backends which don't support scalable vector types from iterating over scalable types. Reviewers: sdesmalen, greened Reviewed By: greened Differential Revision: https://reviews.llvm.org/D66339 llvm-svn: 372099
* [AMDGPU]: PHI Elimination hooks added for custom COPY insertion. FixedAlexander Timofeev2019-09-173-15/+84
| | | | | | | Defferential Revision: https://reviews.llvm.org/D67101 Reviewers: rampitec, vpykhtin llvm-svn: 372086
* AMDGPU/GlobalISel: Fail select of G_INSERT non-32-bit sourceMatt Arsenault2019-09-161-4/+16
| | | | | | | This was producing an illegal copy which would hit an assert later. Error on selection for now until this is implemented. llvm-svn: 371993
* AMDGPU/GlobalISel: Fix RegBankSelect for G_FRINT and G_FCEILMatt Arsenault2019-09-161-0/+2
| | | | llvm-svn: 371991
* AMDGPU/GlobalISel: Select SMRD loads for more typesMatt Arsenault2019-09-161-3/+12
| | | | llvm-svn: 371954
* AMDGPU/GlobalISel: RegBankSelect for killMatt Arsenault2019-09-161-0/+4
| | | | llvm-svn: 371953
* AMDGPU/GlobalISel: Legalize s1 source G_[SU]ITOFPMatt Arsenault2019-09-161-1/+2
| | | | llvm-svn: 371952
* AMDGPU/GlobalISel: Set type on vgpr live in special argumentsMatt Arsenault2019-09-161-1/+2
| | | | | | | Fixes assertion with workitem ID intrinsics used in non-kernel functions. llvm-svn: 371951
* AMDGPU/GlobalISel: Select S16->S32 fptointMatt Arsenault2019-09-162-3/+3
| | | | llvm-svn: 371950
* AMDGPU/GlobalISel: Select s32->s16 G_[US]ITOFPMatt Arsenault2019-09-161-2/+2
| | | | llvm-svn: 371949
* AMDGPU/GlobalISel: Fix VALU s16 fnegMatt Arsenault2019-09-161-0/+10
| | | | llvm-svn: 371948
* Revert for: [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.Alexander Timofeev2019-09-133-50/+5
| | | | llvm-svn: 371873
* [Alignment] Introduce llvm::Align to MCSectionGuillaume Chatelet2019-09-131-1/+1
| | | | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet, JDevlieghere Subscribers: arsenm, sdardis, jvesely, nhaehnle, sbc100, hiraditya, aheejin, jrtc27, atanasyan, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67486 llvm-svn: 371831
* AMDGPU/GlobalISel: Fix assert on multi-return side effect intrinsicsMatt Arsenault2019-09-131-1/+1
| | | | | | llvm.amdgcn.else hits this. llvm-svn: 371812
* AMDGPU/GlobalISel: Legalize s32->s16 G_SITOFP/G_UITOFPMatt Arsenault2019-09-131-1/+1
| | | | llvm-svn: 371811
* AMDGPU/GlobalISel: Fix RegBankSelect for amdgcn.elseMatt Arsenault2019-09-131-0/+7
| | | | llvm-svn: 371808
* AMDGPU/GlobalISel: Select 16-bit VALU bit opsMatt Arsenault2019-09-131-3/+3
| | | | llvm-svn: 371807
* AMDGPU/GlobalISel: Legalize G_FFLOORMatt Arsenault2019-09-132-2/+3
| | | | llvm-svn: 371803
* AMDGPU/GlobalISel: Legalize G_FMADMatt Arsenault2019-09-133-0/+36
| | | | | | | | | | | | | | | Unlike SelectionDAG, treat this as a normally legalizable operation. In SelectionDAG this is supposed to only ever formed if it's legal, but I've found that to be restricting. For AMDGPU this is contextually legal depending on whether denormal flushing is allowed in the use function. Technically we currently treat the denormal mode as a subtarget feature, so custom lowering could be avoided. However I consider this to be a defect, and this should be contextually dependent on the controllable rounding mode of the parent function. llvm-svn: 371800
* AMDGPU/GlobalISel: Select G_CTPOPMatt Arsenault2019-09-134-2/+15
| | | | llvm-svn: 371798
* DAG/GlobalISel: Correct type profile of bitcount opsMatt Arsenault2019-09-131-1/+1
| | | | | | | | The result integer does not need to be the same width as the input. AMDGPU, NVPTX, and Hexagon all have patterns working around the types matching. GlobalISel defines these as being different type indexes. llvm-svn: 371797
* AMDGPU: Inline constant when materalizing FI with add on gfx9Matt Arsenault2019-09-122-3/+6
| | | | | | | | | This was relying on the SGPR usable for the carry out clobber to also be used for the input. There was no carry out on gfx9. With no carry out clobber to worry about, so the literal can just be directly used with a VOP2 add. llvm-svn: 371791
* AMDGPU: Fix bug in r371671 on some builds.Austin Kerbow2019-09-121-2/+5
| | | | llvm-svn: 371761
* AMDGPU: Move m0 initializations earlierAustin Kerbow2019-09-111-4/+38
| | | | | | | | | | | | | | | | | Summary: After hoisting and merging m0 initializations schedule them as early as possible in the MBB. This helps the scheduler avoid hazards in some cases. Reviewers: rampitec, arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67450 llvm-svn: 371671
* [AMDGPU] Fix crash in phi-elimination hook.Michael Liao2019-09-111-2/+4
| | | | | | | | | | | | | | Summary: - Pre-check in case there's just a single PHI insn. Reviewers: alex-t, rampitec, arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, dstuttard, tpr, t-tye, hiraditya, llvm-commits, yaxunl Tags: #llvm Differential Revision: https://reviews.llvm.org/D67451 llvm-svn: 371649
* [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes ↵Guillaume Chatelet2019-09-112-2/+2
| | | | | | | | | | | | | | | | | | | | | | mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
* GlobalISel/TableGen: Handle REG_SEQUENCE patternsMatt Arsenault2019-09-101-14/+36
| | | | | | | | The scalar f64 patterns don't work yet because they fail on multiple results from the unused implicit def of scc in the result bit operation. llvm-svn: 371542
* AMDGPU/GlobalISel: Select G_FABS/G_FNEGMatt Arsenault2019-09-102-52/+92
| | | | | | | | | | | f64 doesn't work yet because tablegen currently doesn't handlde REG_SEQUENCE. This does regress some multi use VALU fneg cases since now the immediate remains in an SGPR, and more moves are used for legalizing the xor. This is a SIFixSGPRCopies deficiency. llvm-svn: 371540
* AMDGPU/GlobalISel: Select cvt pk intrinsicsMatt Arsenault2019-09-102-14/+25
| | | | llvm-svn: 371539
* AMDGPU/GlobalISel: Select llvm.amdgcn.sffbhMatt Arsenault2019-09-102-2/+6
| | | | llvm-svn: 371538
* AMDGPU/GlobalISel: RegBankSelect for G_ZEXTLOAD/G_SEXTLOADMatt Arsenault2019-09-102-3/+11
| | | | llvm-svn: 371536
* AMDGPU/GlobalISel: Legalize constant 32-bit loadsMatt Arsenault2019-09-102-0/+18
| | | | | | | Legalize by casting to a 64-bit constant address. This isn't how the DAG implements it, but it should. llvm-svn: 371535
* AMDGPU/GlobalISel: First pass at attempting to legalize load/storesMatt Arsenault2019-09-103-83/+285
| | | | | | | | There's still a lot more to do, but this handles decomposing due to alignment. I've gotten it to the point where nothing crashes or infinite loops the legalizer. llvm-svn: 371533
* [Alignment][NFC] Use llvm::Align for TargetLowering::getPrefLoopAlignmentGuillaume Chatelet2019-09-102-12/+12
| | | | | | | | | | | | | | | | | | | Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Reviewed By: courbet Subscribers: wuzish, arsenm, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, MaskRay, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67386 llvm-svn: 371511
* [AMDGPU]: PHI Elimination hooks added for custom COPY insertion.Alexander Timofeev2019-09-103-5/+48
| | | | | | | | Reviewers: rampitec, vpykhtin Differential Revision: https://reviews.llvm.org/D67101 llvm-svn: 371508
* AMDGPU/GlobalISel: Fix insert point when lowering fminnum/fmaxnumMatt Arsenault2019-09-091-1/+1
| | | | llvm-svn: 371471
* AMDGPU/GlobalISel: Rename MIRBuilder to B. NFCAustin Kerbow2019-09-094-139/+136
| | | | | | | | | | | | | | Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 llvm-svn: 371467
* AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR v2s16Matt Arsenault2019-09-092-34/+64
| | | | | | | | Handle it the same way as G_BUILD_VECTOR_TRUNC. Arguably only G_BUILD_VECTOR_TRUNC should be legal for this, but G_BUILD_VECTOR will probably be more convenient in most cases. llvm-svn: 371440
* AMDGPU: Make VReg_1 size be 1Matt Arsenault2019-09-093-5/+17
| | | | | | | This was getting chosen as the preferred 32-bit register class based on how TableGen selects subregister classes. llvm-svn: 371438
* AMDGPU/GlobalISel: Select llvm.amdgcn.classMatt Arsenault2019-09-095-1/+32
| | | | | | Also fixes missing SubtargetPredicate on f16 class instructions. llvm-svn: 371436
* AMDGPU/GlobalISel: Select fmed3Matt Arsenault2019-09-094-1/+37
| | | | llvm-svn: 371435
* AMDGPU: Use PatFrags to allow selecting custom nodes or intrinsicsMatt Arsenault2019-09-091-10/+39
| | | | | | | | | | | | | | | | | This enables GlobalISel to handle various intrinsics. The custom node pattern will be ignored, and the intrinsic will work. This will also allow SelectionDAG to directly select the intrinsics, but as they are all custom lowered to the nodes, this ends up leaving dead code in the table. Eventually either GlobalISel should add the equivalent of custom nodes equivalent, or intrinsics should be directly used. These each have different tradeoffs. There are a few more to handle, but these are easy to handle ones. Some others fail for other reasons. llvm-svn: 371432
* AMDGPU: Move MnemonicAlias out of instruction def hierarchyMatt Arsenault2019-09-094-30/+19
| | | | | | | | | | | | | | | | | | Unfortunately MnemonicAlias defines a "Predicates" field just like an instruction or pattern, with a somewhat different interpretation. This ends up overriding the intended Predicates set by PredicateControl on the pseudoinstruction defintions with an empty list. This allowed incorrectly selecting instructions that should have been rejected due to the SubtargetPredicate from patterns on the instruction definition. This does remove the divergent predicate from the 64-bit shift patterns, which were already not used for the 32-bit shift, so I'm not sure what the point was. This also removes a second, redundant copy of the 64-bit divergent patterns. llvm-svn: 371427
* AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUEMatt Arsenault2019-09-095-1/+48
| | | | | | Handle the simple case that lowers to a constant. llvm-svn: 371424
* AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNCMatt Arsenault2019-09-093-0/+70
| | | | | | | | | | Treat this as legal on gfx9 since it can use S_PACK_* instructions for this. This isn't used by anything yet. The same will probably apply to 16-bit G_BUILD_VECTOR without the trunc. llvm-svn: 371423
* AMDGPU/GlobalISel: Select atomic loadsMatt Arsenault2019-09-092-5/+18
| | | | | | | A new check for an explicitly atomic MMO is needed to avoid incorrectly matching pattern for non-atomic loads llvm-svn: 371418
* AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform constant loadsMatt Arsenault2019-09-091-4/+5
| | | | llvm-svn: 371416
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